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參數資料
型號: U635H64D1K45G1
英文描述: PowerStore 8K x 8 nvSRAM
中文描述: PowerStore 8K的× 8非易失
文件頁數: 7/14頁
文件大小: 149K
代理商: U635H64D1K45G1
U635H64
7
March 31, 2006
STK Control #ML0052
Rev 1.0
Nonvolatile Memory Operations
Mode Selection
E
W
A12 - A0
(hex)
Mode
I/O
Power
Notes
H
X
X
Not Selected
Output High Z
Standby
L
H
X
Read SRAM
Output Data
Active
m
L
L
X
Write SRAM
Input Data
Active
L
H
0000
1555
0AAA
1FFF
10F0
0F0F
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
k, l
k, l
k, l
k, l
k, l
k
L
H
0000
1555
0AAA
1FFF
10F0
0F0E
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
k, l
k, l
k, l
k, l
k, l
k
k:
The six consecutive addresses must be in order listed (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) for a Store cycle or
(0000, 1555, 0AAA, 1FFF,10F0, 0F0E) for a RECALL cycle. W must be high during all six consecutive cycles.
See STORE cycle and RECALL cycle tables and diagrams for further details.
The following six-address sequence is used for testing purposes and should not be used: 0000, 1555, 0AAA, 1FFF, 10F0, 139C.
Activation of nonvolatile cycles does not depend on the state of G.
m: I/O state assumes that G
V
IL
.
l:
No.
PowerStor
e
Power Up RECALL
Symbol
Conditions
Min.
Max.
Unit
Alt.
IEC
24
Power Up RECALL Duration
n, e
t
RESTORE
650
μ
s
25
STORE Cycle Duration
f
t
PDSTORE
the power supply vol-
tage must stay above
3.6 V for at least
10 ms after the start
of the STORE
operation
10
ms
26
Time allowed to Complete SRAM Cycle
f,
e
t
DELAY
1
μ
s
Low Voltage Trigger Level
V
SWITCH
4.0
4.5
V
n:
t
RESTORE
starts from the time V
CC
rises above V
SWITCH
.
相關PDF資料
PDF描述
U635H64S2C25 PowerStore 8K x 8 nvSRAM
U635H64S2C25G1 PowerStore 8K x 8 nvSRAM
U635H64S2C35 PowerStore 8K x 8 nvSRAM
U635H64S2C35G1 PowerStore 8K x 8 nvSRAM
U635H64S2C45 PowerStore 8K x 8 nvSRAM
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