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參數資料
| 型號： | UDA1335H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Universal Serial Bus USB Audio Playback Recording Peripheral APRP |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 14 X 20 MM, 2.80 MM HEIGHT, PLASTIC, SOT-319-2, QFP-64 |
| 文件頁數： | 10/44頁 |
| 文件大小： | 254K |
| 代理商： | UDA1335H |
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1998 Aug 28
10
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio
Playback Recording Peripheral (APRP)
UDA1335H
The Analog-to-Digital Interface (ADIF)
The ADIF is used for sampling an analog input signal from
a microphone or line input and sending the audio samples
to the USB interface. The ADIF consists of a stereo
Programmable Gain Amplifier (PGA), a stereo
Analog-to-Digital Converter (ADC) and Decimation Filters
(DFs). The sample frequency of the ADC is determined by
the ADC clock (see Section “The timing of the
analog-to-digital interface”). The user can also select a
digital serial input instead of an analog input. In this event
the sample frequency is determined by the continuous WS
clock with a range between 5 to 55 kHz. Digital serial input
is possible with four formats (I
2
S-bus, 16, 18 or 20 bits
LSB-justified).
The Programmable Gain Amplifier circuit (PGA)
This circuit can be used for a microphone or line input.
The input audio signals can be amplified by 7 different
gains. The preferred gain is selected during start-up of the
device (configuration map).
The gain settings are given in Table 1.
Table 1
The selectable gains of the PGA
The Analog-to-Digital Converter (ADC)
The stereo ADC of the UDA1335H consists of two
3rd-order Sigma-Delta modulators. They have a modified
Ritchie-coder architecture in a differential switched
capacitor implementation. The oversampling ratio is 128.
Both ADCs can be switched off in power saving mode (left
and right separate). The ADC clock is generated by the
analog PLL or the ADC oscillator.
SETTING
GAIN
3
0
3
9
15
21
27
UNIT
000
001
010
011
100
101
11X
dB
dB
dB
dB
dB
dB
dB
The Decimation Filter (DF)
The decimator filter converts the audio data from 128f
s
down to 1f
s
with a word width of 8, 16 or 24 bits. This data
will be transmitted over the USB as mono or stereo in
1, 2 or 3 bytes/sample. The decimator filters are clocked
by the ADC clock.
The timing of the analog-to-digital interface
The clock source of the ADIF is the analog PLL or the ADC
oscillator. The preferred clock source can be selected
during start-up of the device (configuration map). The ADC
clock used for the ADC and decimation filters is obtained
by dividing the clock signal coming from the analog PLL or
from the ADC oscillator by a factor Q.
Using the analog PLL the user can select 3 clock
frequencies via the microcontroller.
By connecting the appropriate crystal the user can choose
any clock signal between 8.192 and 14.08 MHz via the
ADC oscillator.
Table 2
The analog PLL clock output frequencies
The dividing factor Q can be selected via the
microcontroller. With this dividing factor Q the user can
select a range of ADC clock signals allowing several
different sample frequencies (see Table 3).
FCODE
APLL CLOCK
FREQUENCY (MHz)
00
01
10
11
11.2896
8.1920
12.2880
11.2896
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相關代理商/技術參數 |
參數描述 |
|---|---|
| UDA1338H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Multichannel audio coder-decoder |
| UDA1338H/N1 | 制造商:NXP Semiconductors 功能描述:IC CODEC AUDIO 44QFP |
| UDA1338H/N1,518 | 功能描述:音頻放大器 MULTICHANNEL CODEC RoHS:否 制造商:STMicroelectronics 產品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| UDA1338H/N1,557 | 功能描述:音頻放大器 MULTICHANNEL CODEC RoHS:否 制造商:STMicroelectronics 產品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| UDA1338HB | 功能描述:音頻放大器 MULTICHANNEL CODEC RoHS:否 制造商:STMicroelectronics 產品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
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