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參數資料
| 型號： | UDA1340 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | Codec |
| 英文描述： | Low-voltage low-power stereo audio CODEC with DSP features |
| 中文描述： | 低電壓低功耗立體聲音頻編解碼器與數字信號處理功能 |
| 文件頁數： | 6/24頁 |
| 文件大小： | 154K |
| 代理商： | UDA1340 |
1997 Jul 09
6
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1340
FUNCTIONAL DESCRIPTION
System clock
The UDA1340 accommodates slave mode only, this
means that in all applications the system devices must
provide the system clock. The system frequency is
selectable. The options are 256f
s
, 384f
s
and 512f
s
.
The system clock must be locked in frequency to the digital
interface input signals.
Multiple format input/output interface
The UDA1340 supports the following data input/output
formats:
I
2
S-bus with data word length of up to 20 bits
MSB justified serial format with data word length of up to
20 bits
LSB justified serial format with data word lengths of
16, 18 or 20 bits.
The formats are illustrated in Fig.3. Left and right
data-channel words are time multiplexed.
Analog-to-Digital Converter (ADC)
The stereo ADC of the UDA1340 consists of two
third-order Sigma-Delta modulators. They have a modified
Ritchie-coder architecture in a differential switched
capacitor implementation. The over-sampling ratio is 128.
Decimation filter (ADC)
The decimation from 128f
s
is performed in two stages.
The first stage realizes 3rd-order
characteristic. This
filter decreases the sample rate by 16. The second stage,
an FIR filter, consists of 3 half-band filters, each
decimating by a factor of 2.
Table 1
Decimation filter characteristics
ITEM
CONDITION
0
0.45f
s
>0.55f
s
0
0.45f
s
overall
VALUE (dB)
±
0.05
60
108
1.16
Passband Ripple
Stop band
Dynamic range
Gain
x
sin x
DC cancellation filter (ADC)
An optional IIR high-pass filter is provided to remove
unwanted DC components. The operation is selected by
the microcontroller via the L3-bus. The filter characteristics
are given in Table 2.
Table 2
DC cancellation filter characteristics
Mute (ADC)
On recovery from power-down or switching on of the
system clock, the serial data output DATAO is held LOW
until valid data is available from the decimation filter. This
time depends on whether the DC cancellation filter is
selected:
DC cancel off: time =
, t = 23.2 ms when
f
s
= 44.1 kHz
DC cancel on: time =
, t = 279 ms when
f
s
= 44.1 kHz
Overload detection (ADC)
In practice the output is used to indicate whenever the
output data, in either the left or right channel, is greater
than
1 dB (actual figure is
1.16 dB) of the maximum
possible digital swing. When this condition is detected the
OVERFL output is forced HIGH for at least 512f
s
cycles
(11.6 ms at f
s
= 44.1 kHz). This time-out is reset for each
infringement.
ITEM
CONDITION
VALUE (dB)
Passband ripple
Passband gain
Droop
Attenuation at DC
Dynamic range
none
0
0.031
>40
>110
at 0.00045f
s
at 0.00000036f
s
0
0.45f
s
f
s
1024
f
s
12288
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| UDA1341TS/N1,518 | 功能描述:接口—CODEC MINIDISC AUDIO CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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