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參數資料
| 型號： | UDA1342 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | Codec |
| 英文描述： | Audio CODEC |
| 中文描述： | 音頻編解碼器 |
| 文件頁數： | 8/44頁 |
| 文件大小： | 180K |
| 代理商： | UDA1342 |
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2000 Mar 29
8
Philips Semiconductors
Preliminary specification
Audio CODEC
UDA1342TS
8
FUNCTIONAL DESCRIPTION
8.1
System clock
The UDA1342TS operates in slave mode only, this means
that in all applications the system must provide the system
clock. The system clock frequency is selectable and
depends on the mode of operation:
L3-bus/I
2
C-bus mode: 256f
s
, 384f
s
, 512f
s
or 768f
s
Static pin mode: 256f
s
or 384f
s
.
Thesystemclockmustbelockedinfrequencytothedigital
interface signals.
Remarks:
The bit clock frequency f
BCK
can be up to 128f
s
, or in
other words the bit clock frequency is 128 times the
word select frequency f
WS
or less: f
BCK
≤
128f
WS
The WS edge MUST fall on the negative edge of the
BCK signal at all times for proper operation of the digital
interface
The UDA1342TS operates with sample frequencies
from 16 to 110 kHz, however for a system clock of 768f
s
the sampling frequency must be limited to 55 kHz.
8.2
ADC analog front-end
The analog front-end of the UDA1342TS consists of two
stereo ADCs with a programmable gain stage (gain from
0 to 24 dB with 3 dB steps) which can be controlled via the
L3-bus/I
2
C-bus interface.
8.2.1
A
PPLICATION WITH
2 V (RMS)
INPUT
In applications in which a 2 V (RMS) input signal is used,
a15 k
resistormustbeusedinserieswiththeinputofthe
ADC (see Fig.3). This forms a voltage divider together with
the internal ADC resistor and ensures that only 1 V (RMS)
maximum is input to the IC. Using this application for a
2 V (RMS) input signal, the gain switch must be set to
0 dB. When a 1 V (RMS) input signal is input to the ADC in
the same application, the gain switch must be set to 6 dB.
An overview of the maximum input voltages allowed
againstthepresenceof anexternal resistorand thesetting
of the gain switch is given in Table 1.
Table 1
Application modes using input gain stage
handbook, halfpage
VINL1
VDDA(ADC)
VINR1
VADCN
VINL2
VADCP
VINR2
IPSEL
VDDD
VSSD
SYSCLK
L3MODE
L3CLOCK
Vref
VSSA(DAC)
VOUTL
VDDA(DAC)
QMUTE
STATUS
VOUTR
STATIC
TEST1
DATAI
DATAO
WS
BCK
L3DATA
1
2
3
4
5
6
7
8
9
10
11
12
13
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
UDA1342TS
MGT017
Fig.2 Pin configuration.
RESISTOR
(15 k
)
Present
Present
Absent
Absent
PGA GAIN
MAXIMUM INPUT
VOLTAGE
0 dB
6 dB
0 dB
6 dB
2 V (RMS)
1 V (RMS)
1 V (RMS)
0.5 V (RMS)
handbook, halfpage
MGT018
Vref
VINL1,
VINR1,
VINL2,
VINR2
2,
4,
6,
8
gain = 0 dB
10 k
10 k
15 k
input signal
2 V (RMS)
UDA1342TS
Fig.3 Schematic of ADC front-end.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| UDA1342TS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Audio CODEC |
| UDA1342TS/N1 | 制造商:NXP Semiconductors 功能描述:IC CODEC AUDIO MINIDISC 28-SSOP 制造商:NXP Semiconductors 功能描述:IC, CODEC, AUDIO, MINIDISC, 28-SSOP 制造商:NXP Semiconductors 功能描述:IC, CODEC, AUDIO, MINIDISC, 28-SSOP; Audio CODEC Type:Stereo Codec; No. of ADCs:4; No. of DACs:2; No. of Input Channels:4; No. of Output Channels:2; Audio IC Case Style:SSOP; No. of Pins:28; ADC / DAC Resolution:24bit; ADCs / DACs ;RoHS Compliant: Yes |
| UDA1342TS/N1,512 | 功能描述:接口—CODEC AUDIO CODEC MINIDISC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| UDA1342TS/N1,518 | 功能描述:接口—CODEC MINISOUND 3 RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| UDA1342TSDB | 功能描述:接口—CODEC AUDIO CODEC MINIDISC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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