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參數(shù)資料
| 型號： | UDA1350AH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | IEC 958 audio DAC(IEC 958音頻轉(zhuǎn)換器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP44 |
| 封裝： | 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44 |
| 文件頁數(shù)： | 14/36頁 |
| 文件大小： | 154K |
| 代理商： | UDA1350AH |
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1999 Dec 16
14
Philips Semiconductors
Preliminary specification
IEC 958 audio DAC
UDA1350AH
8.6
Control
The UDA1350AH can be controlled by means of static pins or via the L3 interface. For optimum use of the features of
the UDA1350AH the L3 control mode is recommended since only basic functions are available in the static pin control
mode.
It should be noted that the static pin control mode and L3 control mode are mutual exclusive. In the static pin control
mode pins L3MODE and L3DATA are used to select the format for the data output and input interface.
8.6.1
S
TATIC PIN CONTROL MODE
The default values for all non-pin controlled settings are identical to the default values at start-up in the L3 control mode.
Table 3
Pin description of static pin control mode
PIN
NAME
VALUE
FUNCTION
Mode selection pin
35
SELSTATIC
1
select static pin control mode; must be connected to V
DDD
Input pins
1
RESET
0
1
0
00
01
10
11
0
1
0
1
0
1
0
1
normal operation
reset
must be connected to V
SSD
select I
2
S-bus format for digital data interface
select LSB-justified format 16 bits for digital data interface
select LSB-justified format 20 bits for digital data interface
select LSB-justified format 24 bits for digital data interface
normal operation
mute active
select input SPDIF0 (channel 0)
select input SPDIF1 (channel 1)
slave to f
s
from IEC 958; master on data output and input interfaces
slave to f
s
from digital data input interface
select data from digital data interface to DAC output
select data from IEC 958 decoder to DAC output
6
L3CLOCK
L3MODE and
L3DATA
10 and 5
12
MUTE
13
SELCHAN
19
SELCLK
20
SELSPDIF
Status pins
21
LOCK
0
1
00
01
10
11
clock regeneration or IEC 958 decoder out-of-lock
or
non-PCM data detected
clock regeneration and IEC 958 decoder locked
plus
PCM data detected
IEC 958 input: no pre-emphasis
IEC 958 input: f
s
= 32.0 kHz with pre-emphasis
IEC 958 input: f
s
= 44.1 kHz with pre-emphasis
IEC 958 input: f
s
= 48.0 kHz with pre-emphasis
30 and 42 PREEM1 and
PREEM0
Test pins
23
34
39
44
TC
TEST1
TEST2
RTCB
0
1
0
0
must be connected to digital ground (V
SSD
)
must be connected to digital supply voltage (V
DDD
)
must be connected to digital ground (V
SSD
)
must be connected to digital ground (V
SSD
)
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