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參數(shù)資料
| 型號： | UDA1350AH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | IEC 958 audio DAC(IEC 958音頻轉(zhuǎn)換器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP44 |
| 封裝： | 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44 |
| 文件頁數(shù)： | 21/36頁 |
| 文件大小： | 154K |
| 代理商： | UDA1350AH |
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1999 Dec 16
21
Philips Semiconductors
Preliminary specification
IEC 958 audio DAC
UDA1350AH
8.7.8
W
RITABLE REGISTERS
8.7.8.1
Restoring L3 defaults
By writing to the 7FH register, all L3 control values are
restored to their default values. Only the L3 interface is
affected, the system will not be reset. Consequently
readable registers, which are not reset, can be affected.
8.7.8.2
Power-on
A 1-bit value to switch the DAC on and off.
Table 10
Power-on setting
8.7.8.3
Slicer input selection
A 1-bit value to select an IEC 958 input channel.
Table 11
Slicer input selection
8.7.8.4
Clock source selection
A 1-bit value to select the source for clock regeneration,
either from the IEC 958 input or digital data input interface.
In the event that the IEC 958 input is used as a clock
source the UDA1350AH is clock master on the digital data
output and input interfaces.
Table 12
Clock source selection
8.7.8.5
DAC input selection
A 1-bit value to select the data source, either the IEC 958
input or the digital data input interface.
Table 13
DAC input selection
8.7.8.6
Serial format selection
A 2-bit value to set the serial format for the digital data
output and input interfaces.
Table 14
Serial format settings
8.7.8.7
Filter mode selection
A 2-bit value to program the mode for the sound
processing filters of bass boost and treble.
Table 15
Filter mode settings
8.7.8.8
Treble
A 2-bit value to program the treble setting in combination
with the filter mode settings. At f
s
= 44.1 kHz the
3 dB
point for minimum setting is 3.0 kHz and the
3 dB point
for maximum setting is 1.5 kHz. The default value is ‘00’.
Table 16
Treble settings
PON
FUNCTION
0
1
power-down
power-on (default setting)
CHAN sel
FUNCTION
0
IEC 958 input from pin SPDIF0
(default setting)
IEC 958 input from pin SPDIF1
1
IIS sel
FUNCTION
0
slave to audio sampling frequency of
IEC 958 input (default setting)
slave to audio sampling frequency of
digital data input interface
1
SPD sel
FUNCTION
0
1
input from data input interface
input from IEC 958 (default setting)
SFOR1 SFOR0
FUNCTION
0
0
1
1
0
1
0
1
I
2
S-bus (default settings)
LSB-justified, 16 bits
LSB-justified, 20 bits
LSB-justified, 24 bits
M1
M0
FUNCTION
0
0
1
1
0
1
0
1
flat (default setting)
minimum
maximum
TR1
TR0
LEVEL
FLAT (dB)
MIN. (dB)
MAX. (dB)
0
0
1
1
0
1
0
1
0
0
0
0
0
2
4
6
0
2
4
6
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相關(guān)代理商/技術(shù)參數(shù) |
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| UDA1351H/N1,557 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 96 KHZ SPDIF DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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