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參數資料
型號: UDA1360TS
廠商: NXP SEMICONDUCTORS
元件分類: ADC
英文描述: Low-voltage low-power stereo audio ADC
中文描述: 2-CH 20-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16
封裝: 4.40 MM, PLASTIC, MO-152, SOT-369-1, SSOP-16
文件頁數: 5/16頁
文件大小: 84K
代理商: UDA1360TS
2000 Feb 08
5
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio ADC
UDA1360TS
Table 1
Application modes using input gain stage
Multiple format output interface
The UDA1360TS supports the following data output
formats;
I
2
S-bus with data word length of up to 20 bits
MSB-justifiedserial formatwith datawordlength ofupto
20 bits.
TheoutputformatcanbesetbythestaticSFORpin.When
SFOR is LOW, the I
2
S-bus is selected, when SFOR is set
HIGH the MSB-justified format is selected.
The data formats are illustrated in Fig.4. Left and right data
channel words are time multiplexed.
Decimation filter
The decimation from 128f
s
is performed in two stages.
The first stage realizes 3rd-order sin x/x characteristic.
This filter decreases the sample rate by 16. The second
stage (an FIR filter) consists of 3 half-band filters, each
decimating by a factor of 2.
Table 2
DC cancellation filter characteristics
Mute
On recovery from power-down, the serial data output
DATAO is held LOW until valid data is available from the
decimation filter. This time tracks with the sampling
frequency:
; where f
s
= 44.1 kHz.
Power-down mode
The PWON pin can control the power saving together with
the optional gain switch for 2 V (RMS) or 1 V (RMS) input.
When the PWON pin is set LOW, the ADC is set to
power-down. When PWON is set to HIGH or to half the
power supply, then either 6 dB gain or 0 dB gain in the
analog front-end is selected.
Application modes
The UDA1360TS can be set to different modes using two
3-level pins and one 2-level pin. The selection of modes is
given in Table 3.
Table 3
Mode selection summary
RESISTOR
(12 k
)
Present
Present
Absent
Absent
INPUT GAIN
SWITCH
MAXIMUM INPUT
VOLTAGE
0 dB
6 dB
0 dB
6 dB
2 V (RMS)
1 V (RMS)
1 V (RMS)
0.5 V (RMS)
ITEM
CONDITION
VALUE
(dB)
Pass-band ripple
Pass-band gain
Stop band
Droop
Attenuation at DC
Dynamic range
none
0
60
0.031
>40
>110
>0.55f
s
at 0.00045f
s
at 0.00000036f
s
0 to 0.45f
s
PIN
V
SS
1
2
V
DD
V
DD
SFOR
PWON
FSEL
I
2
S-bus
power-down
256f
s
test mode
0 dB gain
MSB
6 dB gain
384f
s
t
f
s
12288
279 ms
=
=
相關PDF資料
PDF描述
UDA1361 96 kHz sampling 24-bit stereo audio ADC
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UDA1384 Multichannel audio coder-decoder
UDA1384H Multichannel audio coder-decoder
相關代理商/技術參數
參數描述
UDA1361 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:96 kHz sampling 24-bit stereo audio ADC
UDA1361TS 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:96 kHz sampling 24-bit stereo audio ADC
UDA1361TS/N1 制造商:NXP Semiconductors 功能描述:ADC STEREO AUDIO 24BIT 16SSOP 制造商:NXP Semiconductors 功能描述:ADC, STEREO, AUDIO, 24BIT, 16SSOP
UDA1361TS/N1,112 功能描述:音頻模/數轉換器 IC ADC STEREO 7712 24BIT RoHS:否 制造商:Wolfson Microelectronics 轉換速率: 分辨率: ADC 輸入端數量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風格: 封裝 / 箱體: 封裝:
UDA1361TS/N1,118 功能描述:音頻模/數轉換器 IC 24 BIT ADC RoHS:否 制造商:Wolfson Microelectronics 轉換速率: 分辨率: ADC 輸入端數量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風格: 封裝 / 箱體: 封裝:
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