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參數資料
| 型號： | UMA1020M |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | Low-voltage dual frequency synthesizer for radio telephones |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2400 MHz, PDSO20 |
| 文件頁數： | 7/20頁 |
| 文件大小： | 159K |
| 代理商： | UMA1020M |
1995 Jul 06
7
Philips Semiconductors
Product specification
Low-voltage dual frequency
synthesizer for radio telephones
UMA1020AM
Table 4
Fast and normal charge pumps current ratio (note 1)
Note
1.
I
SET
=
; common bias current for charge pumps.
Table 5
Power-down modes
CR1
CR0
I
CPA
4
×
I
SET
4
×
I
SET
4
×
I
SET
4
×
I
SET
I
CPP
4
×
I
SET
4
×
I
SET
2
×
I
SET
2
×
I
SET
I
CPPF
16
×
I
SET
32
×
I
SET
24
×
I
SET
32
×
I
SET
I
CPPF
: I
CPP
4 : 1
8 : 1
12 : 1
16 : 1
0
0
1
1
0
1
0
1
AOFF
POFF
FAST
PRINCIPAL
DIVIDERS
AUXILIARY
DIVIDERS
PUMP
CPA
PUMP
CPP
PUMP
CPPF
1
1
1
0
0
0
1
0
0
1
0
0
X
0
1
X
0
1
OFF
ON
ON
OFF
ON
ON
OFF
OFF
OFF
ON
ON
ON
OFF
OFF
OFF
ON
ON
ON
OFF
ON
ON
OFF
ON
ON
OFF
OFF
ON
OFF
OFF
ON
V
ext
R
Power-down modes
The action of the control inputs on the state of internal
blocks is defined by Table 5.
Note that in Table 5, POFF and AOFF can be either the
software or hardware power-down signals. The dividers
are ON when both hardware and software power-down
signals are at logic 0.
When either synthesizer is reactivated after power-down
the main and reference dividers of that synthesizer are
synchronized to avoid the possibility of random phase
errors on power-up.
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