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參數(shù)資料

型號(hào)：	UT7C138C45GCA
英文描述：	SRAM\|4KX8\|CMOS\| RAD HARD\|PGA\|68PIN\|CERAMIC
中文描述：	靜態(tài)存儲(chǔ)器\| 4KX8 \|的CMOS \| RAD數(shù)據(jù)通信硬\|美巡賽\| 68PIN \|陶瓷
文件頁(yè)數(shù)：	11/21頁(yè)
文件大小：	272K
代理商：	UT7C138C45GCA

Address

R/W

Data in

SCE

PWE

DATA

VALID

LZWE

HZWE

HIGH

IMPEDANCE

Figure 4b. Write Cycle 2: R/W Three-States Data I/Os (Either Port)

Assumptions:

The internal write time of memory is defined by the overlap of CE

LOW and R/W LOW. Both signals must be LOW to initialize a write,

and either signal can terminate a write by going HIGH. The data input

set-up and hold timing should be referenced to the rising edge of the sig-

nal that terminates the write.

2. R/W must be HIGH during all address transactions.

3. Data I/O pins enter high impedance even if OE is held LOW during

write.

Data out

WHWL

相關(guān)PDF資料	PDF描述
UT7C138C45GCC	SRAM\|4KX8\|CMOS\| RAD HARD\|PGA\|68PIN\|CERAMIC
UT7C138C45GCX	SRAM\|4KX8\|CMOS\| RAD HARD\|PGA\|68PIN\|CERAMIC
UT7C138C45GPA	x8 Dual-Port SRAM
UT7C138C45GPC	x8 Dual-Port SRAM
UT7C138C45GPX	x8 Dual-Port SRAM

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
UT7C138C45GCC	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:SRAM\|4KX8\|CMOS\| RAD HARD\|PGA\|68PIN\|CERAMIC
UT7C138C45GCX	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:SRAM\|4KX8\|CMOS\| RAD HARD\|PGA\|68PIN\|CERAMIC
UT7C138C45GPA	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:x8 Dual-Port SRAM
UT7C138C45GPC	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:x8 Dual-Port SRAM
UT7C138C45GPX	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:x8 Dual-Port SRAM

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