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參數資料
| 型號： | V58C2512804SALS5I |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 64M X 8 DDR DRAM, 0.65 ns, PBGA60 |
| 封裝： | MO-207, FBGA-60 |
| 文件頁數： | 1/60頁 |
| 文件大小： | 914K |
| 代理商： | V58C2512804SALS5I |
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V58C2512(804/404/164)SA*I
HIGH PERFORMANCE 512 Mbit DDR SDRAM
4 BANKS X 16Mbit X 8 (804)
4 BANKS X 32Mbit X 4 (404)
4 BANKS X 8Mbit X 16 (164)
V58C2512(804/404/164)SA*I Rev.1.6 May 2007
56
DDR400
DDR333
Clock Cycle Time (tCK2)
7.5 ns
Clock Cycle Time (tCK2.5)
6ns
6 ns
Clock Cycle Time (tCK3)
5ns
6 ns
System Frequency (fCK max)
200 MHz
166 MHz
Features
■ High speed data transfer rates with system frequency
up to 200MHz
■ Data Mask for Write Control
■ Four Banks controlled by BA0 & BA1
■ Programmable CAS Latency: 2, 2.5, 3
■ Programmable Wrap Sequence: Sequential
or Interleave
■ Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
■ Automatic and Controlled Precharge Command
■ Power Down Mode
■ Auto Refresh and Self Refresh
■ Refresh Interval: 8096 cycles/64 ms
■ Available in 60 Ball FBGA AND 66 Pin TSOP II
■ SSTL-2 Compatible I/Os
■ Double Data Rate (DDR)
■ Bidirectional Data Strobe (DQS) for input and output
data, active on both edges
■ On-Chip DLL aligns DQ and DQs transitions with CK
transitions
■ Differential clock inputs CK and CK
■ Power Supply 2.5V ± 0.2V
■ Power Supply 2.6V ± 0.1V for DDR400
■ tRAS lockout supported
■ Concurrent auto precharge option is supported
■ Industrial Temp (TA): -40C to +85C
*Note:
(-5) Supports PC3200 module with 3-3-3 timing
(-6) Supports PC2700 module with 2.5-3-3 timing
Description
The V58C2512(804/404/164)SA*I is a four bank DDR
DRAM organized as 4 banks x 16Mbit x 8 (804), 4 banks x
32Mbit x 4 (404), 4 banks x 8Mbit x 16 (164). The
V58C2512(804/404/164)SA*I achieves high speed data
transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the output
data to a system clock.
All of the control, address, circuits are synchronized
with the positive edge of an externally supplied clock. I/O
transactions are occurring on both edges of DQS.
Operating the four memory banks in an interleaved
fashion allows random access operation to occur at a
higher rate than is possible with standard DRAMs. A se-
quential and gapless data rate is possible depending on
burst length, CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
Package Outline
CK Cycle Time (ns)
Power
Temperature
Mark
JEDEC 66 TSOP II
60 FBGA
-5
-6
Std.
L
-40°C to +85°C
I
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