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參數資料
| 型號： | W156 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數： | 1/13頁 |
| 文件大小： | 167K |
| 代理商： | W156 |
Spread Spectrum System Frequency Synthesizer
W158
Cypress Semiconductor Corporation
Document #: 38-07164 Rev. *A
3901 North First Street
San Jose
CA 95134
Revised December 14, 2002
408-943-2600
Features
Maximized EMI suppression using Cypress’s spread
spectrum technology
Intel CK98 Specification compliant
0.5% downspread outputs deliver up to 10 dB lower EMI
Four skew-controlled copies of CPU output
Eight copies of PCI output (synchronous w/CPU output)
Four copies of 66-MHz fixed frequency 3.3V clock
Two copies of CPU/2 outputs for synchronous memory
reference
Three copies of 16.67-MHz IOAPIC clock, synchronous
to CPU clock
One copy of 48-MHz USB output
Two copies of 14.31818-MHz reference clock
Programmable to 133- or 100-MHz operation
Power management control pins for clock stop and shut
down
Available in 56-pin SSOP
Key Specifications
Supply Voltages:...................................... V
DDQ3
= 3.3V±5%
V
DDQ2
= 2.5V±5%
CPU Output Jitter: ......................................................150 ps
CPUdiv2, IOAPIC Output Jitter: ..................................250 ps
48 MHz, 3V66, PCI Output Jitter:................................500 ps
CPU0:3, CPUdiv2_ 0:1 Output Skew:.........................175 ps
PCI_F, PCI1:7 Output Skew:.......................................500 ps
3V66_0:3, IOAPIC0:2 Output Skew: ...........................250 ps
CPU to 3V66 Output Offset:........... 0.0 to1.5 ns (CPU leads)
3V66 to PCI Output Offset:.......... 1.5 to 3.0 ns (3V66 leads)
CPU to IOAPIC Output Offset: ...... 1.5 to 4.0 ns (CPU leads)
CPU to PCI Output Offset:............. 1.5 to 4.0 ns (CPU leads)
Logic inputs, except SEL133/100#, have 250-k
pull-up
resistors
Table 1. Pin Selectable Frequency
[1]
SEL133/100#
CPU0:3 (MHz)
1
133 MHz
0
100 MHz
Note:
1.
See
Table 2
for complete mode selection details.
Intel is a registered trademark of Intel Corporation.
PCI
33.3 MHz
33.3 MHz
Block Diagram
Pin Configuration
REF0:1
CPU0:3
CPUdiv2_0:1
3V66_0:3
XTAL
OSC
PLL 1
SPREAD#
SEL0
SEL1
SEL133/100#
X2
X1
PCI_F
PCI1:7
IOAPIC0:2
48MHz
PLL2
÷
2
STOP
Clock
Logic
Power
Down
Logic
Three-state
Logic
CPU_STOP#
÷
2/
÷
1.5
STOP
Clock
Logic
÷
2
STOP
Clock
Logic
÷
2
2
4
2
4
1
7
3
1
PCI_STOP#
PWRDWN#
GND
REF0
REF1
VDDQ3
X1
X2
GND
PCI_F
PCI1
VDDQ3
PCI2
PCI3
GND
PCI4
PCI5
VDDQ3
PCI6
PCI7
GND
GND
3V66_0
3V66_1
VDDQ3
GND
3V66_2
3V66_3
VDDQ3
W
VDDQ2
IOAPIC2
IOAPIC1
IOAPIC0
GND
VDDQ2
CPUdiv2_1
CPUdiv2_0
GND
VDDQ2
CPU3
CPU2
GND
VDDQ2
CPU1
CPU0
GND
VDDQ3
GND
PCI_STOP#
CPU_STOP#
PWRDWN#
SPREAD#
SEL1
SEL0
VDDQ3
48MHz
GND
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SEL133/100#
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