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參數資料
| 型號： | W184H |
| 英文描述： | MISCELLANEOUS CLOCK GENERATOR|CMOS|SSOP|24PIN|PLASTIC |
| 中文描述： | 雜項時鐘發生器|的CMOS | SSOP封裝| 24針|塑料 |
| 文件頁數： | 1/9頁 |
| 文件大小： | 126K |
| 代理商： | W184H |
Six Output Peak Reducing EMI Solution
W184
Cypress Semiconductor Corporation
Document #: 38-07157 Rev. **
3901 North First Street
San Jose
CA 95134
Revised September 25, 2001
408-943-2600
Features
Cypress PREMIS
family offering
Generates an EMI optimized clocking signal at the
output
Selectable input to output frequency
Six 1.25%, 3.75%, or 0% down or center spread outputs
One non-Spread reference output
Integrated loop filter components
Operates with a 3.3 or 5V supply
Low power CMOS design
Available in 24-pin SSOP (Shrunk Small Outline
Package)
Outputs may be selectively disabled
Key Specifications
Supply Voltages:...........................................V
DD
= 3.3V±5%
or V
DD
= 5V±10%
Frequency Range: .............................. 8 MHz
≤
F
in
≤
28 MHz
Crystal Reference Range.................... 8 MHz
≤
F
in
≤
28 MHz
Cycle to Cycle Jitter:........................................300 ps (max.)
Selectable Spread Percentage:....................1.25% or 3.75%
Output Duty Cycle: ............................... 40/60% (worst case)
Output Rise and Fall Time: ..................................5 ns (max.)
Table 1. Modulation Width Selection
SS%
W184
Output
W184-5
Output
0
F
in
≥
F
out
≥
F
in
–
1.25%
F
in
+ 0.625%
≥
F
in
≥
–
0.625%
1
F
in
≥
F
out
≥
F
in
–
3.75%
F
in
+ 1.875%
≥
F
in
≥
–
1.875%
Table 2. Frequency Range Selection
FS2
FS1
Frequency Range
0
0
8 MHz
≤
F
IN
≤
10 MHz
10 MHz
≤
F
IN
≤
15 MHz
15 MHz
≤
F
IN
≤
18 MHz
18 MHz
≤
F
IN
≤
28 MHz
0
1
1
0
1
1
Table 3. Output Enable
EN1
EN2
CLK0:4
CLK5
0
0
Low
Low
0
1
Low
Active
1
0
Active
Low
1
1
Active
Active
PREMIS is a trademark of Cypress Semiconductor Corporation.
Simplified Block Diagram
Pin Configuration
Spread Spectrum
Outputs
W184
(EMI suppressed)
3.3 or 5.0V
Oscillator or
Reference Input
Spread Spectrum
W184
(EOutputs
3.3 or 5.0V
XTAL
Input
X1
X2
W
24
23
22
21
20
1
2
3
4
5
6
7
8
9
10
11
12
REFOUT
FS2
X1
X2
GND
SS%
EN2
GND
CLK0
VDD
CLK1
CLK2
SSON#
RESET
FS1
VDD
VDD
NC
EN1
CLK5
VDD
CLK4
GND
CLK3
18
17
19
15
14
16
13
SSOP
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