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參數資料
| 型號： | W207B-H |
| 英文描述： | CPU System Clock Generator |
| 中文描述： | CPU系統時鐘發生器 |
| 文件頁數： | 1/16頁 |
| 文件大小： | 151K |
| 代理商： | W207B-H |
Spread Spectrum FTG for SiS540 and 630 Chipsets
W207B
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
November 16, 2000, rev. *B
408-943-2600
Features
Maximized EMI Suppression using Cypress’s Spread
Spectrum technology
Single-chip system frequency synthesizer for SiS540
and SiS630 core logic chip sets
Three copies of CPU output
Seven copies of PCI output
One 48-MHz output for USB
One 24-/48-MHz selectable output for SIO
Two buffered reference outputs
14 SDRAM outputs provide support for 3 DIMMs SMBus
interface for programming
Key Specifications
CPU Cycle-to-Cycle Jitter: ......................................... 250 ps
CPU to CPU Output Skew: ........................................ 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
CPU to PCI Output Skew (CPU leads): ................... 1 to 4 ns
CPU to SDRAM Output Skew:.................................... 500 ps
V
DDQ3
: .................................................................... 3.3V±5%
V
DDQ2
: .................................................3.3V±5% or 2.5V±5%
Block Diagram
Table 1. Pin Selectable Frequency
FS3 FS2 FS1 FS0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
CPU
(MHz)
66.6
100.2
150.3
133.6
66.8
100.2
100.2
133.3
66.6
83.3
97.0
95.0
95.0
112.0
122.0
122.0
SDRAM
(MHz)
100.0
100.2
100.2
100.2
111.3
133.6
150.3
133.3
66.6
83.3
97.0
95.0
126.7
112.0
91.5
122.0
PC
(MHz)
33.3
33.4
37.6
33.4
33.4
33.4
33.4
33.3
33.3
31.2
32.3
31.7
31.7
37.3
30.5
30.5
SS
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
–0.6%
±0.45%
OFF
±0.45%
OFF
±0.45%
OFF
–0.6%
–0.6%
OFF
–0.6%
±0.45%
OFF
OFF
–0.6%
–0.6%
Pin Configuration
Note:
1.
Internal 100-k
pull-down resistors present on inputs marked with *.
Design should not rely solely on internal pull-down resistors to set
I/O pins LOW.
[1]
VDDQ3
REF1
REF0_2X/FS3
PCI0/FS1
PCI1/FS2
XTAL
OSC
PLL Ref Freq
PLL 1
X2
X1
VDDQ3
PCI2
PCI3
PCI4
PCI5
PCI6
48MHz_2X/FS0
SIO/
CPU3.3#_2.5
PLL2
÷
VDDQ2
VDDQ3
I
2
C
Logic
SDATA
SCLK
CPU0:2
x1/÷2
÷
SDRAM0:13
13
3
VDDQ3
REF0_2X/FS3*
GND
X1
X2
VDDQ3
PCI0/FS1*
PCI1/FS2*
PCI2
GND
PCI3
PCI4
PCI5
PCI6
VDDQ3
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDATA
SCLK
SMBus
{
REF1
VDDQ2
CPU0
CPU1
GND
CPU2
VDDQ3
SDRAM13
SDRAM12
GND
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
SDRAM7
SDRAM6
VDDQ3
SDRAM5
SDRAM4
VDDQ3
48MHz_2X/FS0*
SIO/CPU3.3#_2.5*
W
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
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