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參數(shù)資料
| 型號： | W24512AT-25 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | SRAM |
| 英文描述： | 64K X 8 HIGH SPEED CMOS STATIC RAM |
| 中文描述： | 64K X 8 STANDARD SRAM, 25 ns, PDSO32 |
| 封裝： | 8 X 20 MM, TSOP1-32 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大小： | 214K |
| 代理商： | W24512AT-25 |
W24512A
- 4 -
AC Characteristics,continued
(V
DD
= 5V
±
10%, V
SS
= 0V, T
A
= 0 to 70
°
C)
Read Cycle
PARAMETER
SYM.
W24512A-25
UNIT
MIN.
25
-
-
MAX.
-
25
25
Read Cycle Time
Address Access Time
Chip Select Access Time
T
RC
T
AA
T
ACS1
nS
nS
nS
CS1
CS2
T
ACS2
T
AOE
T
CLZ1
*
-
-
3
25
12
-
nS
nS
nS
Output Enable to Output Valid
Chip Selection to Output in Low Z
CS1
CS2
T
CLZ2
*
T
OLZ
*
T
CHZ1
*
3
0
-
-
-
nS
nS
nS
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
CS1
CS2
12
T
CHZ2
*
T
OHZ*
T
OH
-
-
3
12
12
-
nS
nS
nS
Output Disable to Output in High Z
Output Hold from Address Change
*
These parameters are sampled but not 100% tested.
Write Cycle
PARAMETER
SYM.
W24512A-25
UNIT
MIN.
25
18
MAX.
-
-
Write Cycle Time
Chip Selection to End of Write
T
WC
T
CW1
nS
nS
CS1
CS2
T
CW2
T
AW
T
AS
T
WP
T
WR1
18
18
0
15
0
-
-
-
-
-
nS
nS
nS
nS
nS
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
CS1
,
WE
CS2
T
WR2
T
DW
T
DH
T
WHZ
*
T
OHZ
*
T
OW
0
12
0
-
-
0
-
-
-
nS
nS
nS
nS
nS
nS
Data Valid to End of Write
Data Hold from End of Write
Write to Output in High Z
Output Disable to Output in High Z
Output Active from End of Write
* T
hese parameters are sampled but not 100% tested.
12
12
-
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