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參數(shù)資料
| 型號： | W2465K-70LL |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | SRAM |
| 英文描述： | 8K X 8 CMOS STATIC RAM |
| 中文描述： | 8K X 8 STANDARD SRAM, 70 ns, PDIP28 |
| 封裝： | 0.300 INCH, SKINNY, PLASTIC, DIP-28 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大小： | 228K |
| 代理商： | W2465K-70LL |
W2465
- 4 -
AC Characteristics, continued
(V
DD
= 5V
±
10%, V
SS
= 0V, T
A
= 0 to 70
°
C)
Read Cycle
PARAMETER
SYM.
W2465-70
W2465-10
UNIT
MIN.
MAX.
MIN.
MAX.
Read Cycle Time
T
RC
70
-
100
-
nS
Address Access Time
T
AA
-
70
-
100
nS
Chip Select Access Time
CS1
CS2
T
ACS
1
-
70
-
100
nS
T
ACS
2
-
70
-
100
nS
Output Enable to Output Valid
T
AOE
-
35
-
50
nS
Chip Selection to Output in Low Z
CS1
CS2
T
CLZ1
*
5
-
10
-
nS
T
CLZ2
*
5
-
10
-
nS
Output Enable to Output in Low Z
T
OLZ
*
5
-
5
-
nS
Chip Deselection to Output in High Z
CS1
CS2
T
CHZ1
*
-
30
-
35
nS
T
CHZ2
*
-
30
-
35
nS
Output Disable to Output in High Z
T
OHZ
*
-
30
-
35
nS
Output Hold from Address Change
T
OH
10
-
10
-
nS
* These parameters are sampled but not 100% tested.
Write Cycle
PARAMETER
SYM.
W2465-70
MIN.
70
60
W2465-10
MIN.
100
80
UNIT
MAX.
-
-
MAX.
-
-
Write Cycle Time
Chip Selection to End of Write
T
WC
T
CW1
nS
nS
CS1
CS2
T
CW2
T
AW
T
AS
T
WP
T
WR1
60
60
0
45
0
-
-
-
-
-
80
80
0
60
0
-
-
-
-
-
nS
nS
nS
nS
nS
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
CS1
,
WE
CS2
T
WR2
T
DW
T
DH
T
WHZ
*
T
OHZ
*
T
OW
0
30
0
-
-
0
-
-
-
0
-
-
-
nS
nS
nS
nS
nS
nS
Data Valid to End of Write
Data Hold from End of Write
Write to Output in High Z
Output Disable to Output in High Z
Output Active from End of Write
40
0
-
-
0
30
30
-
30
30
-
* These parameters are sampled but not 100% tested.
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