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參數(shù)資料
| 型號(hào)： | W2465K-70LL |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | SRAM |
| 英文描述： | 8K X 8 CMOS STATIC RAM |
| 中文描述： | 8K X 8 STANDARD SRAM, 70 ns, PDIP28 |
| 封裝： | 0.300 INCH, SKINNY, PLASTIC, DIP-28 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大小： | 228K |
| 代理商： | W2465K-70LL |
W2465
- 6 -
Timing Waveforms, continued
Write Cycle 1
Address
OE
CS1
CS2
WE
(1, 4)
D
OUT
D
IN
T
WR1
T
WC
T
CW1
T
CW2
T
WR2
T
WP
T
AS
T
OHZ
T
DW
T
DH
T
AW
Write Cycle 2
(OE = V
IL
Fixed)
Address
CS1
CS2
WE
(2)
(3)
D
OUT
D
IN
T
DW
T
DH
T
OW
T
OH
T
WR2
T
WC
T
CW1
T
WR1
T
CW2
T
AW
T
WP
T
AS
T
WHZ(1, 4)
Notes:
1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.
2. The data output from D
OUT
are the same as the data written to D
IN
during the write cycle.
3. D
OUT
provides the read data for the next address.
4. Transition is measured
±
500 mV from steady state with C
L
= 5 pF. This parameter is guaranteed but not 100% tested.
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