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參數資料
| 型號： | W25S243A-12 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| 中文描述： | 64K的爆流水線× 64高速CMOS靜態RAM |
| 文件頁數： | 3/17頁 |
| 文件大小： | 303K |
| 代理商： | W25S243A-12 |
Preliminary W25S243A
Publication Release Date: November 1998
- 3 -
Revision A1
PIN DESCRIPTION
SYMBOL
TYPE
DESCRIPTION
A0
A15
I/O1
I/O64
CLK
Input, Synchronous
Host address
I/O, Synchronous
Data Inputs/Outputs
Input, Clock
Processor host bus clock
CE1, CE2, CE3
Input, Synchronous
Chip enables
GW
Input, Synchronous
Global write
BWE
Input, Synchronous
Byte write enable from cache controller
BW1
BW8
Input, Synchronous
Host bus byte enables used with BWE
Output enable input
OE
Input, Asynchronous
ADV
Input, Synchronous
Internal burst address counter advance
ADSC
Input, Synchronous
Address status from Chip Set
ADSP
ZZ
Input, Synchronous
Address status from CPU
Input, Asynchronous
Snooze pin for low-power state, internal pull low
FT
Input, Static
Connected to V
SSQ
: Device operates in flow-
through (non-pipelined) mode
.
Connected to V
DDQ
or unconnected
:
Device
operates in pipelined mode
.
LBO
Input, Static
Lower address burst order
Connected to V
SSQ
: Device is in linear mode.
Connected to V
DDQ
or unconnected: Device is in
non-linear mode.
V
DDQ
I/O power supply
V
SSQ
I/O ground
V
DD
Power supply
V
SS
Ground
RSV
Reserved pin, don't use these pins
NC
No connection
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