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參數資料
| 型號： | W25S243A-12 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| 中文描述： | 64K的爆流水線× 64高速CMOS靜態RAM |
| 文件頁數： | 9/17頁 |
| 文件大小： | 303K |
| 代理商： | W25S243A-12 |
Preliminary W25S243A
Publication Release Date: November 1998
- 9 -
Revision A1
AC Timing Characteristics, continued
PARAMETER
SYMBOL
W25S243A-12
MIN.
2.5
UNIT
NOTES
MAX.
-
ADSP
Setup Time
T
ADSS
nS
ADSP
Hold Time
T
ADSH
0.5
-
nS
ADSC
Setup Time
T
ADCS
2.5
-
nS
ADSC
Hold Time
T
ADCH
0.5
-
nS
CE1
, CE2,
CE3
Setup Time
T
CES
2.5
-
nS
CE1
, CE2,
CE3
Hold Time
T
CEH
0.5
-
nS
GW
,
BWE
X Setup Time
T
WS
2.5
-
nS
GW
,
BWE
X Hold Time
Clock Cycle Time
Clock High Pulse Width
Clock Low Pulse Width
Clock to Output Valid
Clock to Output High-Z
Clock to Output Low-Z
Clock to Output Invalid
Output Enable to Output
Valid
Output Enable to Output
High-Z
Output Enable to Output
Low-Z
Output Enable to Output
Invalid
ZZ Standby Time
ZZ Recover Time
T
WH
0.5
-
nS
T
CYC
T
KO
T
KL
T
KQ
T
KHZ
T
KLZ
T
KX
T
OE
15
6
6
-
2
0
2
-
-
-
-
nS
nS
nS
nS
nS
nS
nS
nS
12
15
-
-
7
1
1
1
T
OHZ
-
7
nS
1
T
OLZ
0
-
nS
1
T
OX
0
-
nS
T
ZZS
T
ZZR
-
100
-
nS
nS
2
3
100
Notes:
1. These parameters are sampled but not 100% tested
2. In the ZZ mode, the SRAM will enter a low-power state. In this mode, data retention is guaranteed and the clock is active.
3. ADSC and ADSP should not be accessed for at least 100 nS after chip leaves ZZ mode.
4. Configuration signals LBO and FT are static and should not be changed during operation.
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相關代理商/技術參數 |
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| W25S243AD-12 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| W25S243AF-12 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
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| W25X10_07 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M-BIT, 2M-BIT, 4M-BIT AND 8M-BIT SERIAL FLASH MEMORY WITH 4KB SECTORS AND DUAL OUTPUT SPI |
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