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參數資料
| 型號： | W25S243A |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| 中文描述： | 64K的爆流水線× 64高速CMOS靜態RAM |
| 文件頁數： | 4/17頁 |
| 文件大?。?/td> | 303K |
| 代理商： | W25S243A |
Preliminary W25S243A
- 4 -
FUNCTIONAL DESCRIPTION
The W25S243A is a synchronous-burst pipelined SRAM designed for use in high-end personal
computers. It supports two burst address sequences for Intel
systems (Interleaved mode) and linear
mode, which can be controlled by the
LBO
pin. The burst cycles are initiated by ADSP or ADSC
and the burst counter is incremented whenever ADV is sampled low. The device can also be
switched to non-pipelined mode if necessary.
BURST ADDRESS SEQUENCE
INTEL SYSTEM (LBO = V
DDQ
)
A[1:0]
A[1:0]
00
01
01
00
10
11
11
10
LINEAR MODE (LBO = V
SSQ
)
A[1:0]
A[1:0]
00
01
01
10
10
11
11
00
A[1:0]
10
11
00
01
A[1:0]
11
10
01
00
A[1:0]
10
11
00
01
A[1:0]
11
00
01
10
External Start Address
Second Address
Third Address
Fourth Address
The device supports several types of write mode operations. BWE and BW [8:1] support individual
byte writes. The BE[7:0] signals can be directly connected to the SRAM BW [8:1]. The GW signal is
used to override the byte enable signals and allows the cache controller to write all bytes to the
SRAM, no matter what the byte write enable signals are. The various write modes are indicated in the
Write Table below. Note that in pipelined mode, the byte write enable signals are not latched by the
SRAM with addresses but with data. In pipelined mode, the cache controller must ensure the SRAM
latches both data and valid byte enable signals from the processor.
TRUTH TABLE
CYCLE
ADDRESS
USED
CE1
CE2
CE3
ADSP
ADSC
ADV
OE
DATA
WRITE*
Unselected
No
1
X
X
X
0
X
X
Hi-Z
X
Unselected
No
0
X
1
0
X
X
X
Hi-Z
X
Unselected
No
0
0
X
0
X
X
X
Hi-Z
X
Unselected
No
0
X
1
1
0
X
X
Hi-Z
X
Unselected
No
0
0
X
1
0
X
X
Hi-Z
X
Begin Read
External
0
1
0
0
X
X
X
Hi-Z
X
Begin Read
External
0
1
0
1
0
X
X
Hi-Z
Read
Continue Read
Next
X
X
X
1
1
0
1
Hi-Z
Read
Continue Read
Next
X
X
X
1
1
0
0
D-Out
Read
Continue Read
Next
1
X
X
X
1
0
1
Hi-Z
Read
Continue Read
Next
1
X
X
X
1
0
0
D-Out
Read
Suspend Read
Current
X
X
X
1
1
1
1
Hi-Z
Read
Suspend Read
Current
X
X
X
1
1
1
0
D-Out
Read
Suspend Read
Current
1
X
X
X
1
1
1
Hi-Z
Read
Suspend Read
Current
1
X
X
X
1
1
0
D-Out
Read
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|---|---|
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相關代理商/技術參數 |
參數描述 |
|---|---|
| W25S243A-12 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| W25S243AD-12 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| W25S243AF-12 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| W25X10 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:The W25X10 (1M-bit), W25X20 (2M-bit), W25X40 (4M-bit) and W25X80 (8M-bit) Serial Flash memories provide a storage solution for systems with limited space, pins and power. |
| W25X10_07 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1M-BIT, 2M-BIT, 4M-BIT AND 8M-BIT SERIAL FLASH MEMORY WITH 4KB SECTORS AND DUAL OUTPUT SPI |
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