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參數資料
型號: W26020AT-25
廠商: WINBOND ELECTRONICS CORP
元件分類: SRAM
英文描述: 128K X 16 High Speed CMOS Static RAM
中文描述: 128K X 16 STANDARD SRAM, 25 ns, PDSO44
封裝: TSOP2-44
文件頁數: 1/10頁
文件大小: 126K
代理商: W26020AT-25
W26020A
128K
×
16 HIGH-SPEED CMOS STATIC RAM
GENERAL DESCRIPTION
The W26020A is a high-speed, low-power CMOS static RAM organized as 131,072
×
16 bits that
operates on a single 5-volt power supply. This device is manufactured using Winbond's high
performance CMOS technology.
The W26020A has an active low chip select, separate upper and lower byte selects, and a fast output
enable. No clock or refreshing is required. Separate byte select controls (
LB
and
UB
) allow
individual bytes to be written and read.
LB
controls I/O1-I/O8, the lower byte.
UB
controls I/O9
I/O16, the upper byte. This device is well suited for use in high-density, high-speed system
applications.
Publication Release Date: July 1998
- 1 -
Revision A3
FEATURES
High speed access time: 20/25 nS (max.)
Low power consumption:
Active: 1.5W (max.)
Single
+
5V power supply
Fully static operation
No clock or refreshing
PIN CONFIGURATION
All inputs and outputs directly TTL compatible
Three-state outputs
Data byte control
LB
(I/O1
I/O8),
UB
(I/O9
I/O16)
Available packages: 44-pin type two TSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A0
A1
A2
A3
A4
CS
I/O1
I/O2
I/O3
I/O4
V
DD
V
SS
I/O5
I/O6
I/O7
I/O8
WE
A5
A6
A7
A8
A16
A9
A10
A11
A12
A13
NC
I/O9
I/O10
I/O11
I/O12
V
DD
V
SS
I/O13
I/O14
I/O15
I/O16
LB
UB
OE
A14
A15
NC
BLOCK DIAGRAM
A0
.
.
A16
I/O1
.
.
I/O16
V
DD
V
SS
DATA I/O
DECODER
CONTROL
UB
CS
OE
WE
LB
CORE
PIN DESCRIPTION
SYMBOL
A0
A16
I/O1
I/O16
CS
WE
OE
LB
UB
V
DD
V
SS
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Select Inputs
Write Enable Input
Output Enable Input
Lower Byte Select I/O1
I/O8
Upper Byte Select I/O9
I/O16
Power Supply
Ground
No Connection
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