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參數資料
| 型號： | W26020AT-25 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | SRAM |
| 英文描述： | 128K X 16 High Speed CMOS Static RAM |
| 中文描述： | 128K X 16 STANDARD SRAM, 25 ns, PDSO44 |
| 封裝： | TSOP2-44 |
| 文件頁數： | 7/10頁 |
| 文件大小： | 126K |
| 代理商： | W26020AT-25 |
W26020A
Publication Release Date: July 1998
- 7 -
Revision A3
Timing Waveforms, continued
Write Cycle 1
(OE Clock)
Address
OE
WE
D
D
T
OUT
IN
WC
WR
T
T
AW
WP
T
AS
DW
T
DH
CW
BW
T
UB/LB
Write Cycle 2
(OE = V
IL
Fixed)
WE
D
T
T
T
T
T
(2)
T
T
CS
T
CW
WR
UB/LB
T
BW
Notes:
1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.
2. The data output from D
OUT
are the same as the data written to D
IN
during the write cycle.
3. D
OUT
provides the read data for the next address.
4. Transition is measured
±
500 mV from steady state with C
L
= 5 pF. This parameter is guaranteed but not 100% tested.
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