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參數資料
| 型號： | W26L010AT-12 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | SRAM |
| 英文描述： | 64K X 16 High Speed CMOS Static RAM |
| 中文描述： | 64K X 16 STANDARD SRAM, 12 ns, PDSO44 |
| 封裝： | TSOP2-44 |
| 文件頁數： | 6/10頁 |
| 文件大小： | 131K |
| 代理商： | W26L010AT-12 |
W26L010A
- 6 -
Timing Waveforms
Read Cycle 1
(Address Controlled,
CS
=
OE
=
UB
=
LB
=
V
IL
,
WE
=
V
IH
)
Address
T
T
T
T
D
OH
AA
RC
OH
OUT
Read Cycle 2
(Chip Select Controlled,
OE
=
V
IL
,
WE
=
V
IH
)
Address
RC
T
T
ACS
T
CS
CHZ
T
CLZ
D
T
BLZ
OUT
UB / LB
T
BHZ
T
OE
OHZ
T
OLZ
T
BA
T
OE
HIGH-Z
HIGH-Z
Notes:
1. WE is high for read cycle.
2. Device is continuously selected.
CS
= OE = LB = Low
CS
= OE = LB = Low
3. Address valid prior to or coincident with CS
transition low.
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