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參數(shù)資料
| 型號： | W26L11 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 64K×16bit CMOS Static RAM(64K×16位CMOS靜態(tài)RAM) |
| 中文描述： | 64K的× 16位的CMOS靜態(tài)RAM（64K的× 16位的CMOS靜態(tài)RAM）的 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 134K |
| 代理商： | W26L11 |
Preliminary W26L11
64K
×
16 CMOS STATIC RAM
Publication Release Date: October 1999
- 1 -
Revision A1
GENERAL DESCRIPTION
The W26L11 is a normal speed, very low power CMOS static RAM organized as 65,536
×
16 bits that
perates on a wide voltage range from 2.7V to 3.6V power supply. The W26L11 is manufactured using
Winbond's high performance CMOS technology.
The W26L11 has an active low chip select, separate upper and lower byte selects, and a fast output
enable. No clock or refreshing is required. Separate byte select controls (LB and UB) allow
individual bytes to be written and read.
LB
controls I/O1-I/O8, the lower byte. UB controls
I/O9
I/O16, the upper byte.
FEATURES
Access time: 70 nS
Low power consumption:
Active: 216mW (max.)
Standby: 54
μ
W (max.)
2.7V to 3.6V supply voltage
Fully static operation
All inputs and outputs directly TTL compatible
Three-state outputs
Battery back-up operation capability
Data retention voltage: 2.0V (min.)
Data byte control
LB (I/O1
I/O8), UB (I/O9
I/O16)
Available packages: 44-pin 400 mil SOJ,
44-pin TSOP
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A2
A1
A0
CS
I/O1
I/O2
I/O3
I/O4
V
DD
V
SS
I/O5
I/O6
I/O7
I/O8
WE
A15
A14
A13
A12
NC
NC
A11
A10
A9
A8
NC
I/O9
I/O10
I/O11
I/O12
V
DD
V
SS
I/O13
I/O14
I/O15
I/O16
LB
UB
OE
A7
A6
A5
44-PIN
BLOCK DIAGRAM
A0
.
.
A15
I/O1
.
.
I/O16
V
DD
V
SS
DATA I/O
DECODER
CONTROL
UB
CS
OE
WE
LB
CORE
PIN DESCRIPTION
SYMBOL
A0
A15
I/O1
I/O16
CS
WE
OE
LB
UB
V
DD
V
SS
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Select Inputs
Write Enable Input
Output Enable Input
Lower Byte Select I/O1
I/O8
Upper Byte Select I/O9
I/O16
Power Supply
Ground
No Connection
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