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參數資料
| 型號： | W27C020P-90 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 256K X 8 ELECTRICALLY ERASABLE EPROM |
| 中文描述： | 256K X 8 EEPROM 12V, 90 ns, PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁數： | 2/14頁 |
| 文件大小： | 160K |
| 代理商： | W27C020P-90 |
Preliminary W27C020
- 2 -
FUNCTIONAL DESCRIPTION
Read Mode
Like conventional UVEPROMs, the W27C020 has two control functions, both of which produce data
at the outputs.
CE is for power control and chip select. OE controls the output buffer to gate data to the output pins.
When addresses are stable, the address access time (T
ACC
) is equal to the delay from CE to output
(T
CE
), and data are available at the outputs T
OE
after the falling edge of OE, if T
ACC
and T
CE
timings
are met.
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half
an hour), the W27C020 uses electrical erasure. Generally, the chip can be erased within 100 mS by
using an EPROM writer with a special erase algorithm.
Erase mode is entered when V
PP
is raised to V
PE
(14V), V
CC
= V
CE
(5V), CE = V
IL
, (0.8V or below
but higher than GND), OE = V
IH
(2V or above but lower than V
CC
), A9 = V
ID
(14V), A0 = V
IL,
and all
other address pins equal V
IL
and data input pins equal V
IH
. Pulsing PGM low starts the erase
operation.
Erase Verify Mode
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase
margin. This mode will be entered after the erase operation if V
PP
= V
PE
(14V), CE = V
IL
, and OE =
V
IL,
PGM = V
IH.
Program Mode
Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only
way to change cell data from "1" to "0." The program mode is entered when V
PP
is raised to V
PP
(12V), V
CC
= V
CP
(5V), CE = V
IL
, OE = V
IH
, the address pins equal the desired addresses, and the
input pins equal the desired inputs. Pulsing PGM low starts the programming operation.
Program Verify Mode
All of the bytes in the chip must be verified to check whether they have been successfully
programmed with the desired data or not. Hence, after each byte is programmed, a program verify
operation should be performed. The program verify mode automatically ensures a substantial
program margin. This mode will be entered after the program operation if V
PP
= V
PP
(12V), CE = V
IL,
OE = V
IL,
and
PGM = V
IH
.
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
data. When CE = V
IH
, erasing or programming of non-target chips is inhibited, so that except for the
CE, the W27C020 may have common inputs.
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