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參數資料
| 型號： | W3E32M64S-XSBX |
| 英文描述： | DDR SDRAM STACKED MCP |
| 中文描述： | DDR SDRAM的MCP的堆疊 |
| 文件頁數： | 1/17頁 |
| 文件大小： | 542K |
| 代理商： | W3E32M64S-XSBX |
1
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
January 2004 Rev. 0
W3E32M64S-XSBX
Advanced*
32Mx64 DDR SDRAM
FEATURES
DDR SDRAM rate = 200, 250, 266
Package:
208 Plastic Ball Grid Array (PBGA),
13 x 22mm
2.5V ±0.2V core power supply
2.5V I/O (SSTL_2 compatible)
Differential clock in puts (CK and CK)
Commands entered on each positive CK
edge
Internal pipelined double-data-rate (DDR)
ar chi ec ure; two data accesses per clock
cy cle
Programmable Burst length: 2,4 or 8
Bidirectional data strobe (DQS) transmitted/
re ceived with data, i.e., source-syn chro nous
data capture (one per byte)
DQS edge-aligned with data for READs;
center-aligned with data for WRITEs
DLL to align DQ and DQS transitions with
CLK
Four internal banks for concurrent operation
Data mask (DM) pins for masking write data
(one per byte)
Programmable IOL/IOH option
Auto precharge option
Auto Refresh and Self Refresh Modes
Commercial, Industrial and Military
TemperatureRang es
Organized as 32M x 64
Weight: W3E32M64S-XSBX - 2 grams typical
* Advanced data sheet describes a product that is developmental, non-quali
fi
ed
and is subject to change of cancellation without notice.
BENEFITS
73% SPACE SAVINGS vs. TSOP
-43% Space Savings vs FPBGA
Re duced part count
21% I/O reduction vs TSOP
-13% I/O reduction vs FPBGA
Re duced trace lengths for low er par a sit c
ca pac ance
Suit able for hi-re i abil y ap pli ca ions
Lam nate in er pos er for op i mum TCE match
Upgradeable to 64M x 64 den si y (con act
fac o y for information)
GENERAL DESCRIPTION
The 256MByte (2Gb) DDR SDRAM is a high-speed
CMOS, dy nam c ran dom-access, memory using 4 chips
containing 536,870,912 bits. Each chip is internally
configured as a quad-bank DRAM.
The 256MB DDR SDRAM uses a double data rate
ar chi ec ure to achieve high-speed operation. The
double data rate ar chi ec ure is essentially a 2n-prefetch
architecture with an in er ace designed to transfer two
data words per clock cycle at the I/O pins. A single read
or write access for the 256MB DDR SDRAM effectively
consists of a single 2n-bit wide, one-clock-cycle data
tansfer at the internal DRAM core and two cor e spond ng
n-bit wide, one-half-clock-cycle data transfers at the I/O
pins.
A bi-directional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at the
receiver.strobe transmitted by the DDR SDRAM during
READs and by the memory contoller during WRITEs.
DQS is edge-aligned with data for READs and center-
aligned with data for WRITEs. Each chip has two data
strobes, one for the lower byte and one for the upper
byte.
The 256MB DDR SDRAM operates from a differential
clock (CK and CK); the crossing of CK going HIGH
and CK going LOW will be referred to as the positive
edge of CK. Com mands (ad dress and control signals)
are registered at every positive edge of CK. Input data
is registered on both edg es of DQS, and out put data
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相關代理商/技術參數 |
參數描述 |
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| W3E32M72S-200BC | 制造商:Microsemi Corporation 功能描述:32M X 72 DDR, 2.5V, 200 MHZ, 219 PBGA, COMMERCIAL TEMP. - Bulk |
| W3E32M72S-200BI | 制造商:Microsemi Corporation 功能描述:32M X 72 DDR, 2.5V, 200 MHZ, 219 PBGA, INDUSTRIAL TEMP. - Bulk |
| W3E32M72S-200BM | 制造商:Microsemi Corporation 功能描述:32M X 72 DDR, 2.5V, 200 MHZ, 219 PBGA, MIL-TEMP. - Bulk |
| W3E32M72S-200SBC | 制造商:Microsemi Corporation 功能描述:32M X 72 DDR, 2.5V, 200 MHZ, 208 PBGA, COMMERCIAL TEMP. - Bulk |
| W3E32M72S-200SBI | 制造商:Microsemi Corporation 功能描述:32M X 72 DDR, 2.5V, 200 MHZ, 208 PBGA, INDUSTRIAL TEMP. - Bulk |
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