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參數(shù)資料
| 型號： | W3E64M72S-333SBI |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM, 0.7 ns, PBGA219 |
| 封裝： | 25 X 32 MM, PLASTIC, BGA-219 |
| 文件頁數(shù)： | 1/19頁 |
| 文件大小： | 496K |
| 代理商： | W3E64M72S-333SBI |
W3E64M72S-XSBX
1
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
September 2007
Rev. 3
White Electronic Designs Corp. reserves the right to change products or specications without notice.
64Mx72 DDR SDRAM
FEATURES
Data rate = 200, 250, 266 and 333Mbs**
Package:
219 Plastic Ball Grid Array (PBGA), 25 x 32mm
2.5V ±0.2V core power supply
2.5V I/O (SSTL_2 compatible)
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge
Internal pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
Programmable Burst length: 2,4 or 8
Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (one per byte)
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
DLL to align DQ and DQS transitions with CK
Four internal banks for concurrent operation
Data mask (DM) pins for masking write data
(one per byte)
Auto precharge option
Auto Refresh and Self Refresh Modes
Commercial, Industrial and Military
TemperatureRanges
Organized as 64M x 72
Weight: W3E64M72S-XSBX - 4.5 grams typical
* This product is subject to change without notice. This product has been qualied
for commercial and industrial temperature ranges.
** For 333Mbs operation of Industrial temperature CL = 2.5, at Military temperature
CL = 3.
BENEFITS
66% Space Savings vs. TSOP
Reduced part count
55% I/O reduction vs TSOP
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
GENERAL DESCRIPTION
The 512MByte (4Gb) DDR SDRAM is a high-speed CMOS,
dynamic random-access, memory using 9 chips containing
536,870,912 bits. Each chip is internally configured as a
quad-bank DRAM.
The 512MB DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access for the 512MB DDR SDRAM effectively consists
of a single 2n-bit wide, one-clock-cycle data tansfer at the
internal DRAM core and two corresponding n-bit wide,
one-half-clock-cycle data transfers at the I/O pins.
A bi-directional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at the
receiver.strobe transmitted by the DDR SDRAM during
READs and by the memory contoller during WRITEs. DQS
is edge-aligned with data for READs and center-aligned
with data for WRITEs. Each chip has two data strobes, one
for the lower byte and one for the upper byte.
The 512MB DDR SDRAM operates from a differential clock
(CK and CK#); the crossing of CK going HIGH and CK#
going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered
at every positive edge of CK. Input data is registered on
both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3E64M72S-XBX | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64Mx72 DDR SDRAM |
| W3EG128M72ETSU202AJD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM UNBUFFERED ECC w/PLL |
| W3EG128M72ETSU202D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM UNBUFFERED ECC w/PLL |
| W3EG128M72ETSU202JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM UNBUFFERED ECC w/PLL |
| W3EG128M72ETSU262AJD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR SDRAM UNBUFFERED ECC w/PLL |
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