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參數(shù)資料
| 型號： | WED2DL32512V35 |
| 英文描述： | 512Kx32 Synchronous Pipeline Burst SRAM(高速低功耗CMOS，3.5ns,512Kx32 同步流水線脈沖靜態(tài)RAM) |
| 中文描述： | 512Kx32同步管道爆裂的SRAM（高速低功耗的CMOS，3.5ns，512Kx32同步流水線脈沖靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 1/9頁 |
| 文件大小： | 143K |
| 代理商： | WED2DL32512V35 |
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED2DL32512V
J anuary 2000 Rev. 0
DESCRIPTION
The WEDC SyncBurst - SRAM famly employs high-speed, low-
power CMOS designs that are fabricated using an advanced CMOS
process. WEDC’s 16Mb SyncBurst SRAMs integrate two 512K x 16
SRAMs into a single BGA package to provide 512K x 32 configura-
tion. All synchronous inputs pass through registers controlled by a
positive-edge-triggered single-clock input (CLK). The synchronous
inputs include all addresses, all data inputs, active LOW chip enable
(CE), burst control input (ADSC) and byte write enables (BW
0-3
).
Asynchronous inputs include the output enable (OE), clock (CLK)
and snooze enable (ZZ). There is also a burst mode input (MODE)
that selects between interleaved and linear burst modes. Write cycles
can be fromone to four bytes wide, as controlled by the write control
inputs. Burst operation can be initiated with the address status
controller (ADSC) input.
* Ths datasheet describes aproduct under deveopment, not fuly
characterized andis subect to changewthout notice
512Kx32 Synchronous Pipeline Burst SRAM
PRELIMINARY*
FEATURES
I
Fast clock speed: 200, 166, 150 & 133MHz
I
Fast access times: 2.5ns, 3.5ns, 3.8ns & 4.0ns
I
Fast OE access times: 2.5ns, 3.5ns, 3.8ns 4.0ns
I
Single +3.3V power supply (V
DD
)
I
Separate +3.3V or +2.5V isolated output buffer supply (V
DDQ
)
I
Snooze Mode for reduced-power standby
I
Single-cycle deselect
I
Common data inputs and data outputs
I
Individual Byte Write control and Global Write
I
Clock-controlled and registered addresses, data I/Os and control signals
I
Burst control (interleaved or linear burst)
I
Packaging:
119-bump BGA package
I
Low capacitive bus loading
FIG. 1
BLOCK DIAGRAM
PIN CONFIGURATION
(TOP VIEW)
1
2
3
4
5
6
7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
c
DQ
c
V
DDQ
DQ
c
DQ
c
V
DDQ
DQ
d
DQ
d
V
DDQ
DQ
d
DQ
d
NC
NC
V
DDQ
SA
SA
SA
NC
DQ
c
DQ
c
DQ
c
DQ
c
V
DD
DQ
d
DQ
d
DQ
d
DQ
d
NC
SA
NC
DC
SA
SA
SA
V
SS
V
SS
V
SS
BW
c
V
SS
NC
V
SS
BW
d
V
SS
V
SS
V
SS
MODE
SA
DC
NC
ADSC
V
DD
NC
CE
OE
NC
NC
V
DD
CLK
NC
BWE
SA1
SA0
V
DD
SA
DC
SA
SA
SA
V
SS
V
SS
V
SS
BW
b
V
SS
NC
V
SS
BW
a
V
SS
V
SS
V
SS
NC
SA
DC
SA
SA
SA
NC
DQ
b
DQ
b
DQ
b
DQ
b
V
DD
DQ
a
DQ
a
DQ
a
DQ
a
NC
SA
NC
NC
V
DDQ
NC
NC
DQ
b
DQ
b
V
DDQ
DQ
b
DQ
b
V
DDQ
DQ
a
DQ
a
V
DDQ
DQ
a
DQ
a
NC
ZZ
V
DDQ
DQ
b
DQ
a
SA
CLK
ADSC
OE
BWE
CE
MODE
ZZ
BW
a
BW
b
512K x 16
SSRAM
DQ
d
DQ
c
512K x 16
SSRAM
BW
c
BW
d
NOTE: DC = Do Not Connect
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WED2DL32512V35BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SYNC SRAM|512KX32|CMOS|BGA|119PIN|PLASTIC |
| WED2DL32512V38BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512Kx32 Synchronous Pipeline Burst SRAM |
| WED2DL32512V38BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SYNC SRAM|512KX32|CMOS|BGA|119PIN|PLASTIC |
| WED2DL32512V40BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SYNC SRAM|512KX32|CMOS|BGA|119PIN|PLASTIC |
| WED2DL32512V40BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512Kx32 Synchronous Pipeline Burst SRAM |
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