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參數資料
| 型號： | WED2ZL361MS50BC |
| 英文描述： | 1M x 36 Synchronous Pipeline Burst NBL SRAM(1M x 36,5.0ns同步脈沖流水線靜態RAM(無總線等待時間）) |
| 中文描述： | 100萬× 36同步管道爆裂NBL的靜態存儲器（100萬x 36,5.0納秒同步脈沖流水線靜態隨機存儲器（無總線等待時間）） |
| 文件頁數： | 1/12頁 |
| 文件大小： | 212K |
| 代理商： | WED2ZL361MS50BC |
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED2ZL361MS
J anuary 2001 Rev. 3
ECO #13706
DESCRIPTION
The WEDC SyncBurst - SRAM famly employs high-speed, low-
power CMOS designs that are fabricated using an advanced CMOS
process. WEDC’s 32Mb SyncBurst SRAMs integrate two 1M x 18
SRAMs into a single BGA package to provide 1M x 36 configuration.
All synchronous inputs pass through registers controlled by a
positive-edge-triggered single-clock input (CLK). The NBL or No
Bus Latency Memory utilizes all the bandwidth in any combination
of operating cycles. Address, data inputs, and all control signals
except output enable and linear burst order are synchronized to input
clock. Burst order control must be tied “High or Low.” Asynchro-
nous inputs include the sleep mode enable (ZZ). Output Enable
controls the outputs at any given time. Write cycles are internally
self-timed and initiated by the rising edge of the clock input. This
feature elimnates complex off-chip write pulse generation and
provides increased timng flexibility for incomng signals.
NOTE: Ths datasheet is subect to changewthout notice
1M x 36 Synchronous Pipeline Burst NBL SRAM
FIG. 1
BLOCK DIAGRAM
PIN CONFIGURATION
(TOP VIEW)
Address Bus
(SA
0
– SA
19
)
DQa, DQb
DQPa, DQPb
DQc, DQd
DQPc, DQPd
DQa
–
DQd
DQPa
–
DQPd
1M x 18
1M x 18
CLK
ADV
LBO
CS1
CS2
CS2
OE
WE
ZZ
CLK
CKE
LBO
CE1
CE2
CE2
OE
WE
ZZ
CLK
CKE
LBO
CS1
CS2
CS2
OE
WE
ZZ
B
B
B
B
FEATURES
I
Fast clock speed: 166, 150, 133, and 100MHz
I
Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns
I
Fast OE access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns
I
Single +2.5V
±
5% power supply (V
DD
)
I
Snooze Mode for reduced-standby power
I
Individual Byte Write control
I
Clock-controlled and registered addresses, data I/Os and
control signals
I
Burst control (interleaved or linear burst)
I
Packaging:
119-bump BGA package
I
Low capacitive bus loading
1
2
3
4
5
6
7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DD
SA
NC
DQ
c
DQ
c
V
DD
DQ
c
DQ
c
V
DD
DQ
d
DQ
d
V
DD
DQ
d
DQ
d
NC
NC
V
DD
SA
CE2
SA
DQP
c
DQ
c
DQ
c
DQ
c
DQ
c
V
DD
DQ
d
DQ
d
DQ
d
DQ
d
DQP
d
SA
NC
NC
SA
SA
SA
V
SS
V
SS
V
SS
BW
c
V
SS
NC
V
SS
BW
d
V
SS
V
SS
V
SS
LBO
SA
NC
SA
ADV
V
DD
NC
CE1
OE
SA
WE
V
DD
CLK
NC
CKE
SA1
SA0
V
DD
SA
NC
SA
SA
SA
V
SS
V
SS
V
SS
BW
b
V
SS
NC
V
SS
BW
a
V
SS
V
SS
V
SS
NC
SA
NC
SA
CE2
SA
DQP
b
DQ
b
DQ
b
DQ
b
DQ
b
V
DD
DQ
a
DQ
a
DQ
a
DQ
a
DQP
a
SA
NC
NC
V
DD
NC
NC
DQ
b
DQ
b
V
DD
DQ
b
DQ
b
V
DD
DQ
a
DQ
a
V
DD
DQ
a
DQ
a
NC
ZZ
V
DD
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