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參數(shù)資料
| 型號(hào)： | WED3DL324V12BC |
| 英文描述： | 4Mx32 Synchronous DRAM 3.3V(83MHz,3.3V,4M x32同步動(dòng)態(tài)RAM) |
| 中文描述： | 4Mx32同步DRAM 3.3（83MHz，3.3，4分X32號(hào)，同步動(dòng)態(tài)內(nèi)存） |
| 文件頁(yè)數(shù)： | 1/27頁(yè) |
| 文件大小： | 576K |
| 代理商： | WED3DL324V12BC |
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1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED3DL324V
November 1999
ECO #
4Mx32 SDRAM
FEATURES
I
53% Space Savings vs. Monolithic Solution
I
Reduced System Inductance and Capacitance
I
Pinout and Footprint Compatible to SSRAM 119 BGA
I
3.3V Operating Supply Voltage
I
Fully Synchronous to Positive Clock Edge
I
Clock Frequencies of 125MHz and 83MHz
I
Burst Operation
Sequential or Interleave
Burst Length = Programmable 1, 2, 4, 8 or Full Page
Burst Read and Write
Multiple Burst Read and Single Write
I
Data Mask Control Per Byte
I
Auto and Self Refresh
I
Automatic and Controlled Precharge Commands
I
Suspend Mode and Power Down Mode
I
119 Pin BGA, JEDEC MO-163
FIG. 1
*NOTE:
Pin B3 is designated as NC/A
12
. This pin is used for future density upgrades as address pin A
12
.
PIN DESCRIPTION
PIN CONFIGURATION
ADVANCED*
* This data sheet describes a product that may or may not be under development
and is subject to change or cancellation without notice.
DESCRIPTION
The WED3DL324V is a 4Mx32 Synchronous DRAM configured as
4x1Mx32. The SDRAM BGA is constructed with two 4Mx16 SDRAM
die mounted on a multi-layer laminate substrate and packaged in
a 119 lead, 14mm by 22mm, BGA.
The WED3DL324V is an ideal memory solution for the Texas
Instruments’ TMS320C6000 family of 32 bit DSPs providing a
direct interface to the SDRAM port of the TMS320C6201/C6701and
the combined memory ports of the TMS320C6202, C6203, C6204,
C6205, C6211 and C6711. The compatibility with the SSRAM
119BGA footprint allows for a single systems design to utilize
either SSRAM or SDRAM.
The WED3DL324V is available in clock speeds of 125MHz, 100MHz
and 83MHz. The range of operating frequencies, programmable
burst lengths and programmable latencies allow the same device
to be useful for a variety of high bandwidth, high performance
memory system applications.
The package and design provides performance enhancements via
a 50% reduction in capacitance vs. two monolithic devices. The
design includes internal ground and power planes which reduces
inductance on the ground and power pins allowing for improved
decoupling and a reduction in system noise.
1
2
3
4
5
6
A
7
NC
A
8
NC
DQ
B
DQ
B
DQ
B
DQ
B
V
DD
DQ
A
DQ
A
DQ
A
DQ
A
NC
A
2
NC
NC
6
7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
C
DQ
C
V
DDQ
DQ
C
DQ
C
V
DDQ
DQ
D
DQ
D
V
DDQ
DQ
D
DQ
D
NC
NC
V
DDQ
1
NC
NC
NC
NC
DQ
C
DQ
C
DQ
C
DQ
C
V
DD
DQ
D
DQ
D
DQ
D
DQ
D
NC
A
6
NC
NC
2
BA
0
NC
CAS
V
DD
NC
CE
RAS
NC
CKE
V
DD
CLK
NC
WE
A
1
A
0
V
DD
A
4
NC
4
A
10
A
11
A
9
V
SS
V
SS
V
SS
DQMB
V
SS
NC
V
SS
DQMA
V
SS
V
SS
V
SS
NC
A
3
NC
5
V
DDQ
NC
NC
DQ
B
DQ
B
V
DDQ
DQ
B
DQ
B
V
DDQ
DQ
A
DQ
A
V
DDQ
DQ
A
DQ
A
NC
NC
V
DDQ
7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
NC/A
12
*
BA
1
V
SS
V
SS
V
SS
DQMC
V
SS
NC
V
SS
DQMD
V
SS
V
SS
V
SS
NC
A
5
NC
3
A
0–11
BA
0-1
DQ
0-31
CLK
CKE
DQM
RAS
CAS
CE
V
DD
V
DDQ
Address Bus
Bank Select Addresses
Data Bus
Clock
Clock Enable
Data Input/Output Mask
Row Address Strobe
Column Address Strobe
Chip Enable
Power Supply pins, 3.3V
Data Bus Power
Supply pins,3.3V
Ground pins
V
SS
(TOP VIEW)
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