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參數資料
| 型號： | WED3DL328V10BC |
| 英文描述： | 8Mx32 Synchronous DRAM 3.3V(100MHz,3.3V,8M x 32同步動態RAM) |
| 中文描述： | 8Mx32同步DRAM 3.3（100MHz時，3.3伏，8米× 32同步動態RAM）的 |
| 文件頁數： | 1/27頁 |
| 文件大小： | 409K |
| 代理商： | WED3DL328V10BC |
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White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED3DL328V
October 2000 Rev. 0
ECO #13253
8Mx32 SDRAM
FEATURES
I
53% Space Savings vs. Monolithic Solution
I
Reduced System Inductance and Capacitance
I
Pinout and Footprint Compatible to SSRAM 119 BGA
I
3.3V Operating Supply Voltage
I
Fully Synchronous to Positive Clock Edge
I
Clock Frequencies of 125MHz and 83MHz
I
Burst Operation
Sequential or Interleave
Burst Length = Programmable 1, 2, 4, 8 or Full Page
Burst Read and Write
Multiple Burst Read and Single Write
I
Data Mask Control Per Byte
I
Auto and Self Refresh
I
Automatic and Controlled Precharge Commands
I
Suspend Mode and Power Down Mode
I
119 Pin BGA, JEDEC MO-163
The WED3DL328V is an 8Mx32 Synchronous DRAM configured
as 4x2Mx32. The SDRAM BGA is constructed with two 8Mx16
SDRAM die mounted on a multi-layer laminate substrate and
packaged in a 119 lead, 14mm by 22mm, BGA.
The WED3DL328V is an ideal memory solution for the Texas
Instruments’ TMS320C6000 family of 32 bit DSPs providing a
direct interface to the combined memory ports of the TMS320C,
C6211 and C6711. The compatibility with the SSRAM 119BGA
footprint allows for a single systems design to utilize either
SSRAM or SDRAM.
The WED3DL328V is available in clock speeds of 125MHz,
100MHz and 83MHz. The range of operating frequencies, pro-
grammable burst lengths and programmable latencies allow the
same device to be useful for a variety of high bandwidth, high
performance memory system applications.
The package and design provides performance enhancements
via a 50% reduction in capacitance vs. two monolithic devices.
The design includes internal ground and power planes which
reduces inductance on the ground and power pins allowing for
improved decoupling and a reduction in system noise.
FIG. 1
*NOTE:
Pin B3 s designated as NC/A12. This pin s used for future density upgrades as address pin A12.
PIN DESCRIPTION
PIN CONFIGURATION
(TOP VIEW)
PRELIMINARY
DESCRIPTION
A0 – A11
Address Bus
BA0-1
Bank Select Addresses
DQ
Data Bus
CLK
Clock
CKE
Clock Enable
DQM
Data Input/Output Mask
RAS
Row Address Strobe
CAS
Column Address Strobe
CE
Chip Enable
VDD
Power Supply pins, 3.3V
VDDQ
Data Bus Power Supply pins,3.3V
VSS
Ground pins
1
2
3
4
5
6
7
A
VDDQ
NC
BA0
NC
A10
A7
VDDQ
A
B
NC
NC
NC/A12*
CAS
A11
NC
NC
B
C
NC
NC
BA1
VDD
A9
A8
NC
C
D
DQC
NC
VSS
NC
VSS
NC
DQB
D
E
DQC
DQC
VSS
CE
VSS
DQB
DQB
E
F
VDDQ
DQC
VSS
RAS
VSS
DQB
VDDQ
F
G
DQC
DQC
DQMC
NC
DQMB
DQB
DQB
G
H
DQC
DQC
VSS
CKE
VSS
DQB
DQB
H
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
J
K
DQD
DQD
VSS
CLK
VSS
DQA
DQA
K
L
DQD
DQD
DQMD
NC
DQMA
DQA
DQA
L
M
VDDQ
DQD
VSS
WE
VSS
DQA
VDDQ
M
N
DQD
DQD
VSS
A1
VSS
DQA
DQA
N
P
DQD
NC
VSS
A0
VSS
NC
DQA
P
R
NC
A6
NC
VDD
NC
A2
NC
R
T
NC
NC
A5
A4
A3
NC
NC
T
U
VDDQ
NC
NC
NC
NC
NC
VDDQ
U
1
2
3
4
5
6
7
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