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參數(shù)資料
型號(hào): WED416S16030A
英文描述: Industrial SDRAM
中文描述: 工業(yè)內(nèi)存
文件頁數(shù): 1/26頁
文件大小: 273K
代理商: WED416S16030A
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
WE D416S 16030A
J une 2002 Rev. 0
ECO #15332
DESCRIPTION
The WED416S16030A is 268,435,456 bits of synchro-
nous high data rate DRAM organized as 4 x 4,196,304
words x 16 bits. Synchronous design allows precise
cycle control with the use of system clock. I/O transac-
tions are possible on every clock cycle. Range of oper-
ating frequencies, programmable burst lengths and pro-
grammable latencies allow the same device to be use-
ful for a variety of high bandwidth, high performance
memory system applications.
Available in a 54 pin TSOP type II package the
WED416S16030A is tested over the industrial temp
range (-40°C to +85°C) providing a solution for rugged
main memory applications.
*This product is subject to change without notice.
4M x 16 Bits x 4 Banks Synchronous DRAM
FEATURES
Single 3.3V power supply
Fully Synchronous to positive Clock Edge
Clock Frequency = 133, 125, and 100MHz
SDRAM CAS Latency = 2
Burst Operation
Sequential or Interleave
Burst length = programmable 1,2,4,8 or full page
Burst Read and Write
Multiple Burst Read and Single Write
DATA Mask Control per byte
Auto Refresh (CBR) and Self Refresh
8192 refresh cycles across 64ms
Automatic and Controlled Precharge Commands
Suspend Mode and Power Down Mode
Industrial Temperature Range
FIG. 1
P
IN
D
ESCRIPTION
A
0-12
Address Inputs
BA
0
, BA
1
Bank Select Addresses
CE
Chip Select
WE
Write Enable
CLK
Clock Input
CKE
Clock Enable
DQ
0-15
Data Input/Output
L(U)DQM Data Input/Output Mask
RAS
Row Address Strobe
CAS
Column Address Strobe
V
DD
Power (3.3V)
V
DDQ
Data Output Power
V
SS
Ground
V
SSQ
Data Output Ground
NC
No Connection
P
IN
C
ONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ
15
V
SSQ
DQ
14
DQ
13
V
DDQ
DQ
12
DQ
11
V
SSQ
DQ
10
DQ
9
V
DDQ
DQ
8
V
NC/RFU
UDQM
CLK
CKE
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
V
DD
DQ
0
V
DDQ
DQ
1
DQ
2
V
SSQ
DQ
3
DQ
4
V
DDQ
DQ
5
DQ
6
V
SSQ
DQ
7
V
DD
LDQM
WE
CAS
RAS
CE
BA
0
BA
1
A
10
/AP
A
0
A
1
A
2
A
3
V
DD
T
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