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參數資料
| 型號： | WED9LAPC2C16V4BC |
| 英文描述： | 512K x 32 SSRAM / 512K x 64 SDRAM Array(512Kx32同步靜態RAM和512Kx64同步動態RAM陣列) |
| 中文描述： | 512k × 32的的SSRAM /內存為512k × 64陣列（512Kx32同步靜態內存和512Kx64同步動態內存陣列） |
| 文件頁數： | 1/23頁 |
| 文件大小： | 358K |
| 代理商： | WED9LAPC2C16V4BC |
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED9LAPC2C16V4BC
J uly 2000 Rev. 0
ECO #12964
DESCRIPTION
The WED9LAPC2C16V4BC is a 3.3V, 512K x 32 Synchronous
Pipeline SRAM and a 512K x 64 Synchronous DRAM array
packaged in a 21mm x 21mm 192 lead BGA.
The WED9LAPC2C16V4BC provides the memory required for the
CRAM (Control Memory) and VCRAM (Virtual Connection Memory)
memory ports for Lucent’s LUCTAPC640 ATM port controller.
When used in conjunction with the WED9LAPC2B16P8BC, which
provides memory for the BRAM (Buffer Memory) and PRAM
(Pointer Memory) memory ports, the entire memory requirement
of the LUCTAPC640 can be met using these 2 BGA devices.
The WED9LAPC2C16V4BC is 100% tested to the timing require-
ments of the LUCTAPC640’s memory interface timing for both
Commercial and Industrial temperature ranges.
512K x 32 SSRAM / 512K x 64 SDRAM
External Memory Solution for Lucent’s LUCTAPC640 ATM Port Controller
FEATURES
I
Clock speeds:
SSRAM: 100 MHz
SDRAM: 100 MHz
I
100% tested to timing requirements of LUCTAPC640’s memory
interface
I
Packaging:
192 pin BGA, 21mm x 21mm
I
3.3V Operating supply voltage
I
Direct control interface to both the CRAM and VCRAM ports
on the LUCTAPC640
I
62% space savings vs. monolithic solution
I
Reduced system inductance and capacitance
FIG. 1
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
CADDR
CADDR
VCC
CDATA
CDATA
VSS
CDATA
CDATA
VCC
CDATA
CDATA
VSS
CDATA
CDATA
VCC
CADDR
B
CWE
CADDR
CDATA
CDATA
CDATA
CDATA
CDATA
CDATA
CDATA
CDATA
CDATA
CDATA
CDATA
CDATA
CADDR
CADDR
C
COE
CADDR
CDATA
CDATA
CDATA
CDATA
CDATA
CDATA
CDATA
CDATA
CDATA
CDATA
CDATA
CDATA
CADDR
CADDR
D
VSS
CADDR
CADDR
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VSS
CADDR
CADDR
CADDR
E
GCLK
VSS
NC/CADDR19
VCC
VSS
CADDR
CADDR
CADDR
F
VSS
VCDATA_b
VCDATA_b
VCC
VCC
CADDR0
CADDR1
VSS
G
VCDATA_b
VCDATA_b
VCDATA_b
VSS
VCC
VCDATA_a
VCDATA_a
VCDATA_a
H
VCDATA_b
VCDATA_b
VCDATA_b
VSS
VSS
VCDATA_a
VCDATA_a
VCDATA_a
J
VCC
VCDATA_b
VCDATA_b
VSS
VSS
VCDATA_a
VCDATA_a
VCC
K
VCDATA_b
VCDATA_b
VCDATA_b
VCC
VSS
VCDATA_a
VCDATA_a
VCDATA_a
L
VCDATA_b
VCDATA_b
VCDATA_b
VCC
VCC
VCDATA_a
VCDATA_a
VCDATA_a
M
VSS
VCDATA_b
VCDATA_b
VCC
VCC
VCDATA_a
VCDATA_a
VSS
N
VCDATA_b
VCDATA_b
VCDATA_b
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCDATA_a
VCDATA_a
P
VCDATA_b
VCDATA_b
VCDATA_b
VCDATA_b
VCDATA_b
VSS
VCADDR0 VCADDR2
NC/VCADDR10
VCADDR6
VSS
VCDATA_a
VCDATA_a
VCDATA_a
VCDATA_a
VCDATA_a
R
VCC
VCDATA_b
VCDATA_b
VCDATA_b
VCBS
VCADDR8 VCADDR1 VCADDR3
VCADDR4
VCADDR7
VCDATA_a
VCDATA_a
VCDATA_a
VCDATA_a
VCDATA_a
VCC
T
VCDATA_b
VCDATA_b
VSS
VCDATA_b
VCDQM
VCCAS
VCWE
VCRAS
VCADDR5
VCADDR9/AP
VCC
VCDATA_a
VCDATA_a
VSS
VCDATA_a
VCDATA_a
PINOUT CRAM AND VCRAM MCM -- TOP VIEW
NOTES:
1.
2.
Ball E3 is a No Connect and will be used for CADDR19 for upgrade to 1M x 32 CRAM.
Ball P9 is a No Connect and will be used for VCADDR10 for upgrade to 1M x 64 VCRAM.
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| WED9LC6416V-BC | SSRAM/SDRAM MCP |
| WED9LC6816V-BC | SSRAM/SDRAM MCP |
| WED9LC6416V | 128Kx32 SSRAM/4Mx32 SDRAM Array(128Kx32同步靜態RAM和4Mx32同步動態RAM陣列) |
| WED9LC6416V1512BC | 128Kx32 SSRAM/4Mx32 SDRAM |
| WED9LC6416V1512BI | 128Kx32 SSRAM/4Mx32 SDRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| WED9LAPC2C16V8BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512K x 32 SSRAM / 1M x 64 SDRAM |
| WED9LAPC2C16V8BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512K x 32 SSRAM / 1M x 64 SDRAM |
| WED9LAPC3C16V8BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512K x 32 SSRAM / 1M x 64 SDRAM |
| WED9LAPC3C16V8BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512K x 32 SSRAM / 1M x 64 SDRAM |
| WED9LC6416V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128Kx32 SSRAM/4Mx32 SDRAM |
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