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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
HI-RELIABILITY PRODUCT
WEDPNF8M722V-XBX
September 2000 Rev. 0
8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module
Multi-Chip Package
ADVANCED*
FEATURES
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Package:
275 Plastic Ball Grid Array (PBGA), 32mm x 25mm
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Commercial, Industrial and Military Temperature Ranges
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Weight:
WEDPNF8M722V-XBX - 2.5 grams typical
SDRAM PERFORMANCE FEATURES
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Organized as 8M x 72
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High Frequency = 100, 125MHz
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Single 3.3V
±
0.3V power supply
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Fully Synchronous; all signals registered on positive edge of
system clock cycle
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Internal pipelined operation; column address can be changed
every clock cycle
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Internal banks for hiding row access/precharge
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Programmable Burst length 1,2,4,8 or full page
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4096 refresh cycles
FLASH PERFORMANCE FEATURES
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User Configurable as 2Mx8, 1M x16 or 512K x 32
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Access Times of 100, 120, 150ns
32
25
Discrete Approach
11.9
S
A
V
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N
G
S
Area
I/O
Count
5 x 265mm + 2 x 54mm = 1433mm
2
800mm
2
44%
5 x 54 pins + 2 x 48 balls = 366 connections
275 balls
25%
ACTUAL SIZE
22.3
11.9
11.9
11.9
11.9
48
PBGA
6.0
9.0
Note:
Dimensions in millimeters
48
PBGA
6.0
9.0
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3.3 Volt for Read and Write Operations
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1,000,000 Erase/Program Cycles
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Sector Architecture
One 16KByte, two 8KBytes, one 32KByte, and fifteen 64KBytes
in byte mode
One 8K word, two 4K words, one 16K word, and fifteen 32K
word sectors in word mode.
Any combination of sectors can be concurrently erased. Also
supports full chip erase
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Boot Code Sector Architecture (Bottom)
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Embedded Erase and Program Algorithms
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Erase Suspend/Resume
Supports reading data from or programing data to a sector
not being erased
BENEFITS
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44% SPACE SAVINGS
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Reduced part count
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Reduced I/O count
25% I/O Reduction
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Suitable for hi-reliability applications
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SDRAM Upgradeable to 16M x 72 density (contact factory for
information)
* This data sheet describes a product that may or may not be under
development and is subject to change or cancellation without notice.