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參數資料
型號: X40239
廠商: Intersil Corporation
英文描述: Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP
中文描述: 三電壓監測器,葡萄牙,2千比特EEPROM存儲器,以及單/雙副處長
文件頁數: 1/36頁
文件大小: 541K
代理商: X40239
1
FN8115.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X40231, X40233, X40235, X40237, X40239
Integrated System Management IC
Triple Voltage Monitors, POR, 2 kbit
EEPROM Memory, and Single/Dual DCP
FEATURES
Triple Voltage Monitors
—User Programmable Threshold Voltage
—Power-on Reset (POR) Circuitry
—Software Selectable Reset timeout
—Manual Reset Input
2-Wire industry standard Serial Interface
2 kbit EEPROM with Write Protect & Block Lock
TM
Digitally Controlled Potentiometers (DCP)
X4023X Family Selector Guide
—Total Resistance
256 Tap = 100k
,
100 Tap or 64 Tap = 10k
—Nonvolatile wiper position
—Write Protect Function
Single Supply Operation
—2.7V to 5.5V
16 Pin SOIC (300) package
—SOIC
DESCRIPTION
The X4023x family of Integrated System Manage-
ment ICs combine CPU Supervisor functions (V
CC
Power-onpower-on Reset (POR) circuitry, two addi-
tional programmable voltage monitor inputs with soft-
ware and hardware indicators), integrated EEPROM
with Block Lock
TM
protection and one or two Intersil
Digitally Controlled Potentiometers (XDCP). All func-
tions of the X4023x are accessed by an industry
standard 2-Wire serial interface.
APPLICATIONS
The DCP of the X4023x may be utilized to software
control analog voltages for:
– LCD contrast, LCD purity, or Backlight control.
– Power Supply settings such as PWM frequency,
Voltage Trimming or Margining (temperature offset
control).
– Reference voltage setting (e.g. DDR-SDRAM SSTL-2)
The 2 kbit integrated EEPROM may be used to store
ID, manufacturer data, maintenance data and module
definition data.
The programmable POR circuit insures V
CC
is stable
before RESET is removed and protects against
brown-outs and power failures. The programmable
voltage monitors have on-chip independent reference
alarm levels. With separate outputs, the voltage moni-
tors can be used for power-on sequencing.
BLOCK DIAGRAM
X= 256 tap 100 tap 64 Tap
1
3
5
1
7
1
9
1
1
1
1
1
REDATA
COMMAND
DECODE &
CONTROL
LOGIC
SDA
SCL
POWER-ON /
LORESET
CR
REGISTER
PROTECT LOGIC
EEPROM
ARRAY
THRESHOLD
RESET LOGIC
4
GENERATION
V2MON
V
CC
V
SS
VTRIP
1
V3MON
+
-
2 kbit
RESET
Manual Reset (MR)
8
R
H
R
W
V2FAIL
WP
V3FAIL
2
2000 Intersil Inc., Patents Pending (VTRIP
1,2,3
are user programmable)
CWIPER
R
H
R
W
8 - BIT
NONVOLATILE
MEMORY
256 Tap DCP
Optional
64 or 100 Tap DCP
VTRIP
2
VTRIP
3
CWIPER
8 - BIT
NOMEMORY
+
-
+
Data Sheet
April 11, 2005
相關PDF資料
PDF描述
X40420V14IZ-B Dual Voltage Monitor with Intergrated CPU Supervisor
X40420S14IZ-A Dual Voltage Monitor with Intergrated CPU Supervisor
X40420S14IZ-B Dual Voltage Monitor with Intergrated CPU Supervisor
X40420S14Z-A Dual Voltage Monitor with Intergrated CPU Supervisor
X40420S14Z-B Dual Voltage Monitor with Intergrated CPU Supervisor
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