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參數資料
| 型號： | XC17128D |
| 廠商： | Xilinx, Inc. |
| 英文描述： | QPRO Family of XC1700D QML Serial Configuration PROMs(QPRO XC1700D 系列QML系列配置PROM) |
| 中文描述： | QPRO家庭XC1700D QML第串行配置PROM的（QPRO XC1700D系列QML第系列配置可編程） |
| 文件頁數： | 1/9頁 |
| 文件大小： | 87K |
| 代理商： | XC17128D |
February 8, 1999 (Version 2.0)
1
Features
Certified to MIL-PRF-38535 Appendix A QML (Qualified
Manufacturer Listing.)
Also available under the following Standard Microcircuit
Drawings (SMD): 5962-94717 and 5962-95617.
Serial Configuration one-time programmable (OTP)
read-only memory designed to store configuration
bitstreams of Xilinx FPGA devices
On-chip address counter, incremented by each rising
edge on the clock input
Simple interface to the FPGA requires only one user
I/O pin
Cascadable for storing longer or multiple bitstreams
Programmable reset polarity (active High or active Low)
for compatibility with different FPGA solutions
The XQ1701L device is specified on a different
datasheet. It supports the XQ4000EX/XL/XLA fast
configuration mode (15.0 MHz).
Low-power CMOS EPROM process
Available in 5 V version only, the XQ1701L is available
in 3.3V only
Programming support by leading programmer
manufacturers.
Design support using the Xilinx Alliance and
Foundation series software packages.
Description
The XC1700D Hi-rel family of serial configuration PROMs
(SPROMs) provides an easy-to-use, cost-effective method
for storing Xilinx FPGA configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the SPROM. A short access
time after the rising clock edge, data appears on the
SPROM DATA output pin that is connected to the FPGA
DIN pin. The FPGA generates the appropriate number of
clock pulses to complete the configuration. Once config-
ured, it disables the SPROM. When the FPGA is in Slave
Serial mode, the SPROM and the FPGA must both be
clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all SPROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx Alliance or the
Foundation series development systems compiles the
FPGA design file into a standard HEX format which is then
transferred to most commercial PROM programmers.
0
QPRO
TM
Family of XC1700D QML
Serial Configuration PROMs
February 8, 1999 (Version 2.0)
0
8*
Product Specification
R
Figure 1: Simplified Block Diagram (does not show programming circuit)
EPROM
Cell
Matrix
Address Counter
CE
RESET/
OE or
OE/
RESET
DATA
CEO
OE
Output
CLK
V
CC
V
PP
GND
X3185
TC
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