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參數(shù)資料
| 型號： | XRK39351CQ |
| 廠商： | EXAR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER |
| 中文描述： | 39351 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, TQFP-32 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大小： | 84K |
| 代理商： | XRK39351CQ |
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com
xr
XRK39351
3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER
NOVEMBER 2006
GENERAL DESCRIPTION
REV. 1.0.0
The XRK39351 is a low voltage PLL based clock
driver designed for high speed clock distribution
applications.
The XRK39351 has two reference clock inputs, one
LVPECL and the other LVCMOS. The REF_SEL
input selects clock input to be used as the PLL’s
reference source.
The XRK39351 uses PLL technology to frequency
lock its outputs to the clock reference input. The
divider in the feedback path will determine the
frequency of the VCO. The XRK39351 provides 9
LVCMOS outputs that are separated into 4 banks.
Each of the separate output banks can individually
divide down the VCO output frequency. This allows
the XRK39351 to generate a variety of output-to-input
frequency ratios (1:1, 1:2, 1:4, 2:1 and 4:1). All
outputs provide LVCMOS compatible levels while
driving 50
Ω
terminated transmission lines.
The input reference clock can be directly applied to
the output dividers bypassing the PLL when PLL_EN
input is pulled low. This is a test mode intended for
system debug purposes.
The XRK39351 has an output/input frequency range
of 25MHz to 200MHz with the PLL enabled and an
input frequency range of 2MHz to 300MHz when the
PLL is disabled (test mode).
FEATURES
9 LVCMOS Outputs (4 banks)
25 - 200 MHz output frequency range
Fully Integrated PLL
2.5V or 3.3V Operation
Selectable reference clock input, LVCMOS or
LVPECL
150ps max output to output skew
Pin compatible with MPC9351
Industrial temp range:
-40°C to +85°C
32-Lead TQFP Packaging
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRK39351
PLL
Ref
FB
8
4
2
1
0
1
0
1
0
1
0
TCLK
FB_IN
PLL_EN
SELA
SELB
SELC
SELD
OE
QA
QC0
QC1
÷
÷
÷
1
0
PECL
PECL
REF_SEL
VDD
QD4
QD0
QD1
QD2
QD3
QB
1
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRK39351IQ | 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER |
| XRK39653_0611 | 3.3V, 8-OUTPUT ZERO DELAY BUFFER |
| XRK39653 | 3.3V, 8-OUTPUT ZERO DELAY BUFFER |
| XRK39653CQ | 3.3V, 8-OUTPUT ZERO DELAY BUFFER |
| XRK39653IQ | 3.3V, 8-OUTPUT ZERO DELAY BUFFER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRK39351IQ | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER |
| XRK39653 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V, 8-OUTPUT ZERO DELAY BUFFER |
| XRK39653_0611 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V, 8-OUTPUT ZERO DELAY BUFFER |
| XRK39653CQ | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V, 8-OUTPUT ZERO DELAY BUFFER |
| XRK39653IQ | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V, 8-OUTPUT ZERO DELAY BUFFER |
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