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參數資料
| 型號： | XRK4991IJ-5 |
| 廠商： | EXAR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER |
| 中文描述： | 4991 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32 |
| 封裝： | GREEN, PLASTIC, LCC-32 |
| 文件頁數： | 1/12頁 |
| 文件大小： | 98K |
| 代理商： | XRK4991IJ-5 |
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com
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XRK4991
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
OCTOBER 2005
FUNCTIONAL DESCRIPTION
REV. 1.0.1
The XRK4991 is a 3.3V High-Speed Low-Voltage
Programmable Skew Clock Buffer. It is intended for
high-performance computer systems and offers user
selectable control over system clock functions to
optimize timing. Eight outputs, arranged in four
banks, can each drive 50
terminated transmission
lines while delivering minimal and specified output
skews and full-swing Low Voltage TTL logic levels.
Each bank (two outputs per bank) can be individually
selected for one of nine delay or function
configurations through two dedicated tri-level inputs.
These outputs are able to lead or lag the CLKIN input
reference clock by up to 6 time units from their
nominal “zero” skew position. The integrated PLL
allows external load and transmission line delay
effects to be canceled achieving zero delay capability.
Combining the zero delay capability with the
selectable output skew functions, output-to-output
delays of up to
±
12 time units can be created.
The XRK4991’s divide functions (divide-by-two and
divide-by-four) allow distribution of a low-frequency
clock that can be multiplied by two or four at the clock
destination. This feature facilitates clock distribution
while allowing maximum system clock flexibility.
FEATURES
3.75- to 85-MHz output operation
All output pair skew <100 ps typical
Three skew grades
-2 : t
SKEW0
<250ps
-5 : t
SKEW0
<500ps
-7 : t
SKEW0
<700ps
Selectable output functions
Skew adjustments of +/- 6t
U
(up to 18 ns)
Inverted and non-inverted
Operation at
1
/
2
and
1
/
4
input frequency
Operation at 2x and 4x input frequency
Cycle-Cycle Jitter
< 25 ps (rms)
< 200 ps (pk-pk)
Zero input-to-output delay
50% duty-cycle outputs
LVTTL outputs drive 50
terminated lines
Operates from a single 3.3V supply
32-pin PLCC package
Green packaging
Lead free lead frame available
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRK4991
PLL
CLKIN
FB_IN
FSEL*
PLL_BYPASS*
Bank “SKEW”
Control
QA0
QA1
QB0
QB1
QC0
QC1
QD0
QD1
SELA[1:0]*
SELB[1:0]*
SELC[1:0]*
SELD[1:0]*
* Tri-Level inputs
L
M
H
Ref
Feedback
2
2
2
2
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