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| 型號(hào)： | Z80B-CTC |
| 英文描述： | Z8 Microcontrollers |
| 中文描述： | Z8微控制器 |
| 文件頁(yè)數(shù)： | 47/222頁(yè) |
| 文件大?。?/td> | 1595K |
| 代理商： | Z80B-CTC |
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UM001600-Z8X0599
5-1
U
SER
’
S
M
ANUAL
C
HAPTER
5
I/O P
ORTS
5.1 I/O PORTS
The Z8 has up to 32 lines dedicated to input and output.
These lines are grouped into four 8-bit ports known as Port
0, Port 1, Port 2, and Port 3. Port 0 is nibble programmable
as input, output, or address. Port 1 is byte configurable as
input, output, or address/data. Port 2 is bit programmable
as either inputs or outputs, with or without handshake and
SPI. Port 3 can be programmed to provide timing, serial
and parallel input/output, or comparator input/output.
All ports have push-pull CMOS outputs. In addition, the
push-pull outputs of Port 2 can be turned off for open-drain
operation.
5.1.1 Mode Registers
Each port has an associated Mode Register that deter-
mines the port’s functions and allows dynamic change in
port functions during program execution. Port and Mode
Registers are mapped into the Standard Register File as
shown in Figure 5-1.
Because of their close association, Port and Mode Regis-
ters are treated like any other general-purpose register.
There are no special instructions for port manipulation. Any
instruction which addresses a register can address the
ports. Data can be directly accessed in the Port Register,
with no extra moves.
5.1.2 Input and Output Registers
Each bit of Ports 0, 1, and 2, have an input register, an out-
put register, associated buffer, and control logic. Since
there are separate input and output registers associated
with each port, writing to bits defined as inputs stores the
data in the output register. This data cannot be read as
long as the bits are defined as inputs. However, if the bits
are reconfigured as outputs, the data stored in the output
register is reflected on the output pins and can then be
read. This mechanism allows the user to initialize the out-
puts prior to driving their loads (Figure 5-2).
Since port inputs are asynchronous to the Z8 internal
clock, a READ operation could occur during an input tran-
sition. In this case, the logic level might be uncertain
(somewhere between a logic 1 and 0). To eliminate this
meta-stable condition, the Z8 latches the input data two
clock periods prior to the execution of the current instruc-
tion. The input register uses these two clock periods to sta-
bilize to a legitimate logic level before the instruction reads
the data.
Note:
The following sections describe the generic
function of the Z8 ports. Any additional features of the ports
such as SPI, C/T, and Stop-Mode Recovery are covered in
their own section.
Figure 5-1. I/O Ports and Mode Registers
Register
HEX
Port 3 Mode
Port 2 Mode
Identifier
F8H
F7H
F6H
P01M
P3M
P2M
Port 3
Port 0-1 Mode
Port 2
Port 1
Port 0
03H
02H
01H
00H
P3
P2
P1
P0
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