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參數資料
| 型號： | Z84C9008VEC |
| 文件頁數： | 11/31頁 |
| 文件大小： | 491K |
| 代理商： | Z84C9008VEC |
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Port B does not support Mode 2 operation and can only be used in
Mode 3 when Port A is programmed for Mode 2. BRDY is not
associated with Port B when it is operating in Mode 3.
ASTB, BSTB.
Port Strobe (inputs, Active Low). These signals indicate that the peripheral
device has performed a transfer. In Mode 0, the signal indicates that the peripheral device
has accepted the data present on the port pins. In Mode 1, the signal causes the data on the
port pins to be latched onto Port A. In Mode 2, ASTB Low causes the data in the output
data latch of Port A to be placed onto the Port A pins. BSTB Low causes the data present
on the Port A pins to be latched into the Port A input data latch. The end of the current
transaction is noted by the rising edge of these signals.
Port B does not support Mode 2 operation, and can only be used in
Mode 3 when Port A is programmed for Mode 2. BSTB is not
associated with Port B when it is operating in Mode 3.
CLK/TRG0
–
CLK/TRG3.
External Clock/Timer Trigger (inputs, user-selectable Active
High or Low). These four pins correspond to the four counter/timer channels of the KIO.
In Counter mode, each active edge causes the downcounter to decrement. In Timer mode,
an active edge starts the timer.
CLKOUT.
Clock Out (output). This output is a divide-by-two of the oscillator (XTAL)
input.
CLOCK.
System Clock (input). This clock must be the same as (or a derivative of) the
CPU clock. If the CLKOUT is to be used as the system clock, then these two pins must be
connected together.
CS.
Chip Select (input, Active Low). Used to activate the internal register decoding mech-
anism and allow the KIO to perform a data transfer to/from the CPU.
CTSA, CTSB.
Clear to Send (inputs, Active Low). These signals are modem control sig-
nals for the serial channels. When programmed for Auto Enable, a Low on these pins
enables their respective transmitters. If not programmed as Auto Enable, these pins may
be used as general-purpose input signals.
D
0
–
D
7
. Data Bus (bidirectional, Active High, 3-stated). Used for data exchanges between
the CPU and the KIO for programming and data transfer. The KIO also monitors the data
bus for RETI instructions to maintain its Interrupt Under Service (IUS) status.
DCDA
,
DCDB
. Data Carrier Detect (inputs, Active Low). These signals are modem con-
trol signals for the serial channels. When programmed for Auto Enable, a Low on these
pins enables their respective receivers. If not programmed as Auto Enable, these pins may
be used as general-purpose input signals.
DTRA
,
DTRB
. Data Terminal Ready (outputs, Active Low). These signals are modem
control signals for the serial channels. They follow the state programmed into their respec-
tive serial channels, and are multiplexed with Port C, bits 5 and 2, respectively.
%5
%5
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相關代理商/技術參數 |
參數描述 |
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| Z84C9008VEC00TR | 功能描述:IC Z80 MPU KIO 84PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:Z80 標準包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點:- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應商設備封裝:516-PBGAPGE（27x27） 包裝:托盤 |
| Z84C9008VED1380 | 功能描述:IC Z80 KIO TM 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:Z80 標準包裝:60 系列:SCC 處理器類型:Z380 特點:全靜電 Z380 CPU 速度:20MHz 電壓:5V 安裝類型:表面貼裝 封裝/外殼:144-LQFP 供應商設備封裝:144-LQFP 包裝:托盤 |
| Z84C9008VEG | 功能描述:輸入/輸出控制器接口集成電路 8MHz Z80 KIO XTEMP RoHS:否 制造商:Silicon Labs 產品: 輸入/輸出端數量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| Z84C9008VEJ1380TR | 制造商:Zilog 功能描述:ZLGZ84C9008VEJ1380TR Z80 KIO SUPERINTEGR |
| Z84C9008VSC | 功能描述:輸入/輸出控制器接口集成電路 8MHz Z80 KIO RoHS:否 制造商:Silicon Labs 產品: 輸入/輸出端數量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
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