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參數資料
| 型號： | Z84C9008VEC |
| 文件頁數： | 12/31頁 |
| 文件大小： | 491K |
| 代理商： | Z84C9008VEC |
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IEI.
Interrupt Enable In (input, Active High). This signal is used with Interrupt Enable
Out (IEO) to form a priority daisy chain when there is more than one interrupt-driven
device. A High on this line indicates that no higher-priority device is requesting an inter-
rupt.
IEO.
Interrupt Enable Out (output, Active High). This signal is used with Interrupt Enable
In (IEI) to form a priority daisy chain when there is more than one interrupt-driven device.
A High on this line indicates that this device is requesting an interrupt, and that no higher-
priority device, is not requesting an interrupt. A Low blocks any lower-priority devices
from requesting an interrupt.
IORQ.
Input/Output Request (input, Active Low). IORQ is used with RD, A
0
–
A
3
, and CS
to transfer data between the KIO and the CPU. When IORQ, RD, and CS are Active Low,
the device selected by A
0
–
A
3
transfers data to the CPU. When IORQ and CS are Active
Low, but RD is Active High, the device selected by A
0
–
A
3
is written into by the CPU.
When IORQ and M1 are both Active Low, the KIO may respond with an interrupt vector
from its highest-priority interrupting device.
M1.
Machine Cycle 1 (input, Active Low). When M1 and RD are Low, the Z80 CPU
fetches an instruction from memory; the KIO decodes this cycle to determine if the RETI
instruction sequence is being executed. When M1 and IORQ are both active, the KIO
decodes the cycle to be an interrupt acknowledge, and may respond with a vector from its
highest-priority interrupting device.
OSC.
Oscillator (output). This output is a reference clock for the oscillator.
PA0
–
PA7.
Port A Bus (bidirectional, tristated). One of the 8-bit ports of the PIO. PA
0
is
the least-significant bit of the bus.
PB0
–
PB7.
Port B Bus (bidirectional, tristated). One of the 8-bit ports of the PIO. PB
0
is
the least-significant bit of the bus. This port can also supply 1.5mA at 1.5V to drive Dar-
lington transistors.
PC0
–
PC7.
Port C Bus (bidirectional, tristated). PC
0
is the least-significant bit of the bus.
These pins are multiplexed between the 8-bit PIA and additional modem control signals
for the serial channels.
RD.
Read (input, Active Low). When RD is active, a memory or I/O read operation is in
progress. RD is used with A
0
–
A
3
, CS and IORQ to transfer data between the KIO and
CPU.
RESET.
Reset (input, Active Low). A Low on this pin forces the KIO into a Reset condi-
tion. This signal must be active for a minimum of three Clock cycles. The KIO resets so
that the PIO ports operate in Mode 1
7
With handshakes inactive and interrupts disabled
7
PIA port in Input mode and active
7
CTC channel counting terminated and interrupts disabled
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相關代理商/技術參數 |
參數描述 |
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| Z84C9008VEC00TR | 功能描述:IC Z80 MPU KIO 84PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:Z80 標準包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點:- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應商設備封裝:516-PBGAPGE（27x27） 包裝:托盤 |
| Z84C9008VED1380 | 功能描述:IC Z80 KIO TM 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:Z80 標準包裝:60 系列:SCC 處理器類型:Z380 特點:全靜電 Z380 CPU 速度:20MHz 電壓:5V 安裝類型:表面貼裝 封裝/外殼:144-LQFP 供應商設備封裝:144-LQFP 包裝:托盤 |
| Z84C9008VEG | 功能描述:輸入/輸出控制器接口集成電路 8MHz Z80 KIO XTEMP RoHS:否 制造商:Silicon Labs 產品: 輸入/輸出端數量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| Z84C9008VEJ1380TR | 制造商:Zilog 功能描述:ZLGZ84C9008VEJ1380TR Z80 KIO SUPERINTEGR |
| Z84C9008VSC | 功能描述:輸入/輸出控制器接口集成電路 8MHz Z80 KIO RoHS:否 制造商:Silicon Labs 產品: 輸入/輸出端數量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
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