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參數資料
型號: Z9973BA
英文描述: DIODE TVS 15V 500W UNI-DIR
中文描述: 第十二章分布式輸出時鐘驅動器| TQFP封裝| 52PIN |塑料
文件頁數: 3/11頁
文件大小: 63K
代理商: Z9973BA
3.3V, 125MHz, Multi-Output Zero Delay Buffer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07089 Rev. **
9/15/2000
Page 3 of 11
Z9973
Maximum Ratings
Input Voltage Relative to VSS:
Input Voltage Relative to VDD:
Storage Temperature:
Operating Temperature:
Maximum Power Supply:
VSS-0.3V
VDD+0.3V
-65
°
C to + 150
°
C
-40
°
C to +85
°
C
5.5V
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
DC Parameters
Characteristic
Input Low Voltage
Input High Voltage
Peak-to-Peak Input Voltage
PECL_CLK
Common Mode Range PECL_CLK
Symbol
VIL
VIH
VPP
Min
VSS
2.0
300
Typ
Max
Units
Conditions
-
-
-
0.8
VDD
1000
V
V
mV
Note 1
VCMR
VDD-
2.0
-
VDD-
0.6
-120
120
0.5
V
Input Low Current ( @ VIL = VSS)
Input High Current ( @ VIH = VDD)
Output Low Voltage
Output High Voltage
Quiescent Supply Current
PLL Supply Current
Input Pin Capacitance
IIL
IIH
VOL
VOH
IDDC
IDD
Cin
μA
μA
V
V
mA
mA
pF
Note 3
Note 3
IOL = 20mA, Note 2
IOH = -20mA, Note 2
All VDDC and VDD
VDD only
2.4
-
10
15
-
15
20
4
-
VDD = VDDC =3.3V + 5%, TA = -40
°
C to +85
°
C
Note 1:
The VCMR is the difference from the most positive side of the differential input signal. Normal operation is
obtained when the “High” input is within the VCMR range and the input lies within the VPP specification.
Note 2:
Driving series or parallel terminated 50
(or 50
to VDD/2) transmission lines.
Note 3:
Inputs have pull-up/pull-down resistors that affect input current
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相關代理商/技術參數
參數描述
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