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參數(shù)資料
| 型號(hào)： | Z9974CA |
| 英文描述： | DIODE TVS 16V 500W BI-DIR |
| 中文描述： | 共14名分布式輸出時(shí)鐘驅(qū)動(dòng)器| TQFP封裝| 52PIN |塑料 |
| 文件頁(yè)數(shù)： | 4/9頁(yè) |
| 文件大小： | 62K |
| 代理商： | Z9974CA |
3.3V, 125MHz, Multi-Output Zero Delay Buffer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07090 Rev. *A
06/18/2001
Page 4 of 9
Z9974
PIN DESCRIPTION (Cont.)
PIN No.
40,38,36,
34,32
50,48,46,
44
52
Pin Name
Qb(0:4)
I/O
O
Description
High drive, Low Voltage CMOS, Output clock buffers, Bank Qb. Their divide ratio is
programmed by fselb, pin#4.
High drive, Low Voltage CMOS, Output clock buffers, Bank Qc. Their divide ratio is
programmed by fselc, pin#5.
Input select pin for setting the divider of the VCO output. It has a 250K
internal pull-down.
If VCO_sel = 0, then the PLL VCO output is divided by 2. If VCO_sel = 1, then the PLL
VCO output is divided by 4. See fig.1, page2; table 1, page1, table 2, page 3.
These pins are not connected internally. They may be attached to a ground plane.
Power for input logic circuitry.
Ground for input logic circuitry.
Power and Ground supply pins for internal Analog circuitry.
3.3V supply for Qa(0:4) output bank, and fselFB1 input.
Common ground for Qa(0:4) output bank, and fselFB1 input.
Power and ground supply pins for QFB output and FB_In input pins and digital circuitry.
3.3V supply for Qb(0:4) output bank.
Common ground for Qb(0:4) output bank.
3.3V supply for Qc(0:3) output bank and VCO_sel pin.
Common ground for Qc(0:3) output bank and VCO_sel pin.
Analog Ground
Qc(0:3)
O
VCO_Sel
I
11,27,42
12
15
13,
17,22,26
19,24
28, 30
33,37,41
35,39
45,49
43,47,51
1
n/c
VDDI
VSSI
VDDA
VDDa
VSSa
-
P
P
P
P
P
P
P
P
P
P
P
VDDFB / VSSFB
VDDb
VSSb
VDDc
VSSc
VSSA
A bypass capacitor (0.1
μ
F) should be placed as close as possible to each positive power pin (<0.2”). If these bypass
capacitors are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductances of
the traces.
Glitch-Free Output Frequency Transitions
Customarily when zero delay buffers have their internal counter’s changed “on the fly’ their output clock periods will:
A. Contain short or “runt” clock periods. These are clock cycles in which the cycle(s) are shorter in period than either
the old or new frequency that is being transitioned to.
B. Contain stretched clock periods. These are clock cycles in which the cycle(s) are longer in period than either the old
or new frequency that is being transitioned to.
This device specifically includes logic to guarantee that runt and stretched clock pulses do not occur if the device logic
levels of any or all of the following pins changed “on the fly” while it is operating: Fsela, Fselb, Fselc, and VCO_Sel
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