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| 型號： | 61LV256 |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | CONNECTOR ACCESSORY |
| 中文描述： | 連接器附件 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大小： | 100K |
| 代理商： | 61LV256 |
ISSI
IS61LV256
2-4
Integrated Silicon Solution, Inc.
Rev. F 0296
SR81995LV61
AC TEST LOADS
635
30 pF
Including
jig and
scope
702
OUTPUT
3.3V
635
5 pF
Including
jig and
scope
702
OUTPUT
3.3V
Figure 1a.
Figure 1b.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1a and 1b
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-12 ns
Min.
-15 ns
Min.
-20 ns
Min.
-25 ns
Min.
Symbol
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
(2)
t
HZOE
(2)
t
LZCE
(2)
t
HZCE
(2)
t
PU
(3)
t
PD
(3)
Parameter
Max.
Max.
Max.
Max.
Unit
Read Cycle Time
12
—
15
—
20
—
25
—
ns
Address Access Time
—
12
—
15
—
20
—
25
ns
Output Hold Time
2
—
2
—
2
—
2
—
ns
CE
Access Time
—
12
—
15
—
20
—
25
ns
OE
Access Time
—
6
—
7
—
8
—
9
ns
OE
to Low-Z Output
0
—
0
—
0
—
0
—
ns
OE
to High-Z Output
—
7
—
8
—
9
—
10
ns
CE
to Low-Z Output
3
—
3
—
3
—
3
—
ns
CE
to High-Z Output
—
5
—
6
—
9
—
10
ns
CE
to Power-Up
0
—
0
—
0
—
0
—
ns
CE
to Power-Down
—
13
—
15
—
18
—
20
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured
±
500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
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