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參數資料
| 型號： | 61S6432 |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
| 中文描述： | 64K的× 32 SYNCHRONOU擰管道靜態RAM |
| 文件頁數： | 1/19頁 |
| 文件大小： | 140K |
| 代理商： | 61S6432 |
Integrated Silicon Solution, Inc. 1-800-379-4774
Rev.
B
06/28/01
1
IS61S6432
64K x 32 SYNCHRONOUS
PIPELINE STATIC RAM
ISSI
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. Copyright 2001, Integrated Silicon Solution, Inc.
FEATURES
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data and
control
Pentium or linear burst sequence control using
MODE input
Three chip enables for simple depth expansion
and address pipelining
Common data inputs and data outputs
Power-down control by ZZ input
JEDEC 100-Pin TQFP and PQFP package
Single +3.3V power supply
Two Clock enables and one Clock disable to
eliminate multiple bank bus contention
Control pins mode upon power-up:
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GNDQ
or VCCQ to alter their power-up state
Industrial temperature available
DESCRIPTION
The
ISSI
IS61S6432 is a high-speed, low-power
synchronous static RAM designed to provide a burstable,
high-performance, secondary cache for the Pentium,
680X0, and PowerPC microprocessors. It is organized
as 65,536 words by 32 bits, fabricated with
ISSI
's advanced
CMOS technology. The device integrates a 2-bit burst
counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous
inputs pass through registers controlled by a positive-edge-
triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1
controls DQ1-DQ8,
BW2
controls DQ9-DQ16,
BW3
controls DQ17-DQ24,
BW4
controls DQ25-DQ32,
conditioned by
BWE
being LOW. A LOW on
GW
input would
cause all bytes to be written.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally by the IS61S6432 and controlled by the
ADV
(burst address advance) input pin.
Asynchronous signals include output enable (
OE
), sleep
mode input (ZZ), clock (CLK) and burst mode input (MODE).
A HIGH input on the ZZ pin puts the SRAM in the power-
down state. When ZZ is pulled LOW (or no connect), the
SRAM normally operates after three cycles of the wake-up
period. A LOW input, i.e., GND
Q
, on MODE pin selects
LINEAR Burst. A V
CCQ
(or no connect) on MODE pin selects
INTERLEAVED Burst.
JUNE 2001
FAST ACCESS TIME
Symbol
Parameter
-200
(1)
-166
-133
-117
-5
-6
-7
-8
Unit
t
KQ
CLK Access Time
4
5
5
5
5
6
7
8
ns
t
KC
Cycle Time
5
6
7.5
8.5
10
12
13
15
ns
—
Frequency
200
166
133
117
100
83
75
66
MHz
Note:
1. ADVANCE INFORMATION ONLY.
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