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參數資料
| 型號： | 61S6432 |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
| 中文描述： | 64K的× 32 SYNCHRONOU擰管道靜態(tài)RAM |
| 文件頁數： | 8/19頁 |
| 文件大小： | 140K |
| 代理商： | 61S6432 |
PB
Integrated Silicon Solution, Inc.
1-800-379-4774
Rev.
B
06/28/01
IS61S6432
ISSI
READ CYCLE SWITCHING CHARACTERISTICS
(Over Operating Range)
-200
(1)
Min.
-166
-133
-117
Symbol
Parameter
Max.
Min.
Max.
Min.
Max.
Min.
Max
Unit
t
KC
Cycle Time
5
—
6
—
7.5
—
8.5
—
ns
t
KH
Clock High Time
1.6
—
2.4
—
2.8
—
3
—
ns
t
KL
Clock Low Time
1.6
—
2.4
—
2.8
—
3
—
ns
t
KQ
Clock Access Time
—
4
—
5
—
5
—
5
ns
t
KQX
(2)
Clock High to Output Invalid
1
—
1.5
—
1.5
—
1.5
—
ns
t
KQLZ
(2,3)
Clock High to Output Low-Z
0
—
0
—
0
—
0
—
ns
t
KQHZ
(2,3)
Clock High to Output High-Z
1
3.5
1.5
5
1.5
5
1.5
6
ns
t
OEQ
Output Enable to Output Valid
—
3.5
—
5
—
5
—
5
ns
t
OEQX
(2)
Output Disable to Output Invalid
0
—
0
—
0
—
0
—
ns
t
OELZ
(2,3)
Output Enable to Output Low-Z
0
—
0
—
0
—
0
—
ns
t
OEHZ
(2,3)
Output Disable to Output High-Z
—
3
—
3
—
3
—
4
ns
t
AS
Address Setup Time
2
—
2.5
—
2.5
—
2.5
—
ns
t
SS
Address Status Setup Time
2
—
2.5
—
2.5
—
2.5
—
ns
t
WS
Write Setup Time
2
—
2.5
—
2.5
—
2.5
—
ns
t
CES
Chip Enable Setup Time
2
—
2.5
—
2.5
—
2.5
—
ns
t
AVS
Address Advance Setup Time
2
—
2.5
—
2.5
—
2.5
—
ns
t
AH
Address Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
t
SH
Address Status Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
t
WH
Write Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
t
CEH
Chip Enable Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
t
AVH
Address Advance Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
t
CFG
(4)
Configuration Setup
25
—
25
—
30
—
35
—
ns
Notes:
1.
ADVANCE INFORMATION ONLY.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
4. Configuration signal MODE is static and must not change during normal operation.
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