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參數資料
| 型號： | 62C1024L |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 128K x 8 LOW POWER CMOS STATIC RAM |
| 中文描述： | 128K的× 8低功耗CMOS靜態(tài)RAM |
| 文件頁數： | 6/11頁 |
| 文件大小： | 65K |
| 代理商： | 62C1024L |
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. E
11/26/03
IS62C1024L
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range, Standard and Low Power)
-35
-70
Symbol
t
WC
t
SCE
1
t
SCE
2
t
AW
t
HA
t
SA
t
PWE
(4)
t
SD
t
HD
t
HZWE
(2)
t
LZWE
(2)
Parameter
Min.
Max.
Min.
Max.
Unit
Write Cycle Time
35
—
70
—
ns
CE1
to Write End
25
—
60
—
ns
CE2 to Write End
25
—
60
—
ns
Address Setup Time to Write End
25
—
60
—
ns
Address Hold from Write End
0
—
0
—
ns
Address Setup Time
0
—
0
—
ns
WE
Pulse Width
25
—
50
—
ns
Data Setup to Write End
20
—
30
—
ns
Data Hold from Write End
0
—
0
—
ns
WE
LOW to High-Z Output
—
10
—
25
ns
WE
HIGH to Low-Z Output
3
—
5
—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CE1
LOW, CE2 HIGH and
WE
LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
4. Tested with
OE
HIGH.
Notes:
1.
WE
is HIGH for a Read Cycle.
2. The device is continuously selected.
OE
,
CE1
= V
IL
, CE2 = V
IH
.
3. Address is valid prior to or coincident with
CE1
LOW and CE2 HIGH transitions.
READ CYCLE NO. 2
(1,3)
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE1/
t
ACE2
t
LZCE1/
t
LZCE2
t
HZOE
HIGH-Z
DATA VALID
t
HZCE
ADDRESS
OE
CE1
CE2
DOUT
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