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參數資料
| 型號： | 7016S35PFGB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 16K X 9 DUAL-PORT SRAM, 35 ns, PQFP80 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, GREEN, TQFP-80 |
| 文件頁數： | 19/20頁 |
| 文件大小： | 164K |
| 代理商： | 7016S35PFGB |
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
8
tRC
R/
W
CE
ADDR
tAA
OE
3190 drw 07
(4)
tACE
(4)
tAOE
(4)
(1)
tLZ
tOH
(2)
tHZ
(3,4)
tBDD
DATAOUT
BUSYOUT
VALID DATA
(4)
Waveform of Read Cycles(5)
NOTES:
1. Timing depends on which signal is asserted last,
OE or CE.
2. Timing depends on which signal is de-asserted first,
CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last: tAOE, tACE, tAA or tBDD.
5.
SEM = VIH.
Timing of Power-Up / Power-Down
CE
3190 drw 08
tPU
ICC
ISB
tPD
50%
,
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