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參數資料
| 型號： | 7016S35PFGB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 16K X 9 DUAL-PORT SRAM, 35 ns, PQFP80 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, GREEN, TQFP-80 |
| 文件頁數： | 7/20頁 |
| 文件大小： | 164K |
| 代理商： | 7016S35PFGB |
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
15
Waveform of Interrupt Timing(1)
Truth Table III — Interrupt Flag(1)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt truth table.
3. Timing depends on which enable signal (
CE or R/W) is asserted last.
4. Timing depends on which enable signal (
CE or R/W) is de-asserted first.
NOTES:
1. Assumes
BUSYL = BUSYR = VIH.
2. If
BUSYL = VIL, then no change.
3. If
BUSYR = VIL, then no change.
3190 drw 17
ADDR"A"
INTERRUPT SET ADDRESS
CE"A"
R/
W"A"
tAS
tWC
tWR
(3)
(4)
tINS
(3)
INT"B"
(2)
3190 drw 18
ADDR"B"
INTERRUPT CLEAR ADDRESS
CE"B"
OE"B"
tAS
tRC
(3)
tINR
(3)
INT"B"
(2)
Left Port
Right Port
Function
R/
WL
CEL
OEL
A13L-A0L
INTL
R/
WR
CER
OER
A13R-A0R
INTR
L
X
3FFF
X
XXX
X
L(2)
Set Right
INTR Flag
X
XXX
X
L
3FFF
H(3)
Reset Right
INTR Flag
XXX
X
L(3)
L
X
3FFE
X
Set Left
INTL Flag
XL
L
3FFE
H(2)
X
Reset Left
INTL Flag
3190 tbl 16
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