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參數資料
| 型號： | 71M6543G-IGTR/F |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 封裝： | LEAD FREE, LQFP-100 |
| 文件頁數： | 73/157頁 |
| 文件大小： | 2178K |
| 代理商： | 71M6543G-IGTR/F |
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71M6543F/H Data Sheet
8
22
2008-2010 MAXIM/TERIDIAN Semiconductor Corporation
v1.2
2.2.8
71M6xx3 Isolated Sensor Interface
2.2.8.1 General Description
Non-isolating sensors, such as shunt resistors, can be connected to the inputs of the 71M6543 via a
combination of a pulse transformer and a 71M6xx3 IC (a top-level block diagram of this sensor interface
is shown in Figure 31). The 71M6xx3
receives power directly from the 71M6543 via a pulse transformer
and does not require a dedicated power supply circuit. The 71M6xx3 establishes 2-way communication
with the 71M6543, supplying current samples and auxiliary information such as sensor temperature via a
serial data stream.
Up to three 71M6xx3 Isolated Sensors can be supported by the 71M6543. When a remote sensor
interface is enabled, the two analog current inputs become re-configured as a digital remote sensor
interface. For example, when control bit RMT2_E = 1, the IADC2-IADC3 analog pins are re-configured as
the digital interface pins to the remote sensor.
Each 71M6xx3 Isolated Sensor consists of the following building blocks:
Power supply that derives power from pulses received from the 71M6543
Bi-directional digital communications interface
Shunt signal pre-amplifier
22-bit 2nd Order Sigma-Delta ADC Converter with precision bandgap reference (chopping amplifier)
Temperature sensor (for digitally compensating VREF)
Fuse system containing part-specific information
During an ordinary multiplexer cycle, the 71M6543 internally determines which other channels are
enabled with MUX_DIV[3:0] (I/O RAM 0x2100[7:4]). At the same time, it decimates the modulator output
from the 71M6xx3 Isolated Sensors. Each result is written to CE RAM during one of its CE access time
slots.
2.2.8.2 Communication between 71M6543 and 71M6xx3 Isolated Sensor
The ADC of the 71M6xx3 derives its timing from the power pulses generated by the 71M6543 and as a
result, operates its ADC slaved to the frequency of the power pulses. The generation of power pulses, as well
as the communication protocol between the 71M6543 and 71M6xx3 Isolated Sensor, is automatic and
transparent to the user. Details are not covered in this data sheet.
2.2.8.3 Control of the 71M6xx3 Isolated Sensor
The 71M6543 can read or write certain types of information from each 71M6xx3 remote sensor.
The data to be read is selected by a combination of the RCMD[4:0] and TMUXRn[2:0]. To perform a read
transaction from one of the 71M6xx3 devices, the MPU first writes the TMUXRn[2:0] field (where n = 2, 4, 6,
located at I/O RAM 0x270A[2:0], 0x270A[6:4] and 0x2709[2:0], respectively). Next, the MPU writes
RCMD[4:0] (SFR 0xFC[4:0]) with the desired command and phase selection. When the RCMD[4:2] bits
have cleared to zero, the transaction has been completed and the requested data is available in
RMT_RD[15:0] (I/O RAM 0x2602[7:0] is the MSB and 0x2603[7:0] is the LSB). The read parity error bit,
PERR_RD (SFR 0xFC[6]) is also updated during the transaction. If the MPU writes to RCMD[4:0] before a
previously initiated read transaction is completed, the command is ignored. Therefore, the MPU must wait
for RCMD[4:2]=0 before proceeding to issue the next remote sensor read command.
If the CE is running (CE_E=1), the MPU must write RCMD[4:0] immediately after a CE_BUSY rising
edge. RCMD[4:0] must be written before the next rising edge of MUX_SYNC. Failure to do this can cause
incorrect data to be read.
The RCMD[4:0] field is divided into two sub-fields, COMMAND=RCMD[4:2] and PHASE=RCMD[1:0], as
shown in Table 4.
.
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