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參數資料
| 型號： | 73M1903C-IMR/F |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC32 |
| 封裝： | LEAD FREE, QFN-32 |
| 文件頁數： | 15/48頁 |
| 文件大小： | 487K |
| 代理商： | 73M1903C-IMR/F |
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73M1903C Data Sheet
DS_1903C_033
22
Rev. 5.0
6.2
Analog I/O
Figure 7 shows the block diagram of the analog front end. The analog interface circuit uses differential
transmit and receive signals to and from the external circuitry.
The hybrid driver in the 73M1903C is capable of connecting directly, but not limited to, a transformer-
based Direct Access Arrangement (DAA). The hybrid driver is capable of driving the DAA’s line coupling
transformer and load impedance. The hybrid drivers can also drive high impedance loads without
modification.
An on-chip band gap voltage is used to provide an internal voltage reference and bias currents for the
analog receive and transmit channels. The reference derived from the bandgap, nominally 1.25 V, is
multiplied to 1.36 Volts and output at the VREF pin. Several voltage references, nominally 1.25 V, are
used in the analog circuits. The band gap and reference circuits are disabled after a chip reset since the
ENFE (Register00 bit7) is reset to a default state of zero. When ENFE=0, the band gap voltage and the
analog bias currents are disabled. In this case all of the analog circuits are powered down and draw less
than 5 μA of current.
A clock generator (CKGN) is used to create all of the non-overlapping phase clocks needed for the time
sampled switched-capacitor circuits, ASDM, DAC1, and TLPF. The CKGN input is 2 times the
analog/digital interface sample rate or 3.072 MHz clock for Fs=8 kHz.
AMUX1
Out
SE
L
MUX
ASDM
RXAP
AAF
Analog
Sigma-Delta
Modulator
TXAP1
TXAN2
Hybrid Drivers
TLPF
Transmit
Low Pass
Filter
Anti-Alias Filter
DAC
1
Outp
Outn
In
DAC
SFR
REGISTERS
d
tm
fb
s
t
ANALOG
DDEC
Serial
Port
1
15:0
DSDM
1
DIGITAL
gai
n
BGAP
CKGN
PLL/
CLKDIV
sck (3.072 MHz)
phase clocks (1.536 MHz)
phase clocks
(1.536 MHz)
Digital
Sigma-Delta
Modulator
Decimating
Filter
Clocks
rbi
t
tbit
Clock Generator
Bandgap
anal
b
analb
VBG
SMFLT
E
x
t
Loopbk
Int
Loopbk
rbs
tbs
OPSR
RXAN
MUX
D
igLoopbk
v
re
frx
txb
st
v
re
ftx
TXAP2
TXAN1
+
-
Figure 7: Analog Block Diagram
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